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Physical Design Engineer Intern Jobs in Roxbury, MA

Analogdevices

Manufacturing Engineer Intern

Wilmington, MA · On-site

$18.25 - $23.75/hr

ADI) is a global semiconductor leader that bridges the physical and digital worlds to enable ... Collaborate with mechanical design engineers to develop fixturing and improve designs for ...

Analog Devices

Manufacturing Engineer Intern

Wilmington, MA · On-site

$18.25 - $23.75/hr

ADI) is a global semiconductor leader that bridges the physical and digital worlds to enable ... Collaborate with mechanical design engineers to develop fixturing and improve designs for ...

Analogdevices

Manufacturing Engineer Intern

Chelmsford, MA · On-site

$17.50 - $22.50/hr

ADI) is a global semiconductor leader that bridges the physical and digital worlds to enable ... Collaborate with mechanical design engineers to develop fixturing and improve designs for ...

Broadcom Inc.

ASIC Design Engineer

Andover, MA · On-site

$108 - $173/hr

ASIC Design Engineer page is loaded## ASIC Design Engineerlocations: USA-CA Irvine Alton Parkway ... physical design checks.**Responsibilities Include:*** Participate in large complex design ...

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All JobsPhysical Design Engineer Intern JobsPhysical Design Engineer Intern Jobs in Roxbury, MA

Physical Design Engineer Intern information

See Roxbury, MA salary details

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How much do physical design engineer intern jobs pay per hour?

As of Sep 2, 2026, the average hourly pay for physical design engineer intern in Roxbury, MA is $20.96, according to ZipRecruiter salary data. Most workers in this role earn between $17.50 and $22.69 per hour, depending on experience, location, and employer.

What does a physical design engineer intern do?

A Physical Design Engineer Intern assists in the process of transforming a circuit design (RTL) into a real, manufacturable layout for semiconductor chips. They work on tasks such as floorplanning, placement, routing, timing analysis, and verifying that the chip design meets all physical and electrical requirements. Interns typically use electronic design automation (EDA) tools to perform these tasks and collaborate with experienced engineers. Their work is crucial in ensuring that chips are both functional and manufacturable at scale.

What skills and qualifications are needed to thrive as a physical design engineer intern?

To thrive as a Physical Design Engineer Intern, you generally need a solid background in electrical engineering, digital circuit design, and semiconductor fundamentals, often supported by ongoing university studies in a related field. Familiarity with industry-standard EDA tools such as Cadence, Synopsys, or Mentor Graphics, as well as scripting languages like TCL or Python, is highly valuable. Attention to detail, problem-solving abilities, and effective teamwork are crucial soft skills for excelling in this role. These skills and qualifications are important because they ensure accurate chip layouts, efficient workflows, and successful collaboration within complex engineering teams.

What types of projects and tasks can a physical design engineer intern expect to work on during their internship?

As a Physical Design Engineer Intern, you will typically be involved in supporting the design and verification of integrated circuits at the physical level. Common tasks include assisting with floorplanning, placement and routing, timing analysis, and running design rule checks using industry-standard EDA tools. You may also participate in team meetings, collaborate with senior engineers, and help resolve issues related to power, performance, and area optimization. These hands-on experiences are designed to help you build practical skills and gain a deeper understanding of the physical design flow in VLSI chip development.

What is the difference between Physical Design Engineer Intern vs Digital Design Engineer Intern?

AspectPhysical Design Engineer InternDigital Design Engineer Intern
Required CredentialsTypically pursuing or holding a degree in Electrical Engineering or Computer EngineeringTypically pursuing or holding a degree in Electrical Engineering or Computer Engineering
Work EnvironmentDesigning and implementing physical chip layouts, working with EDA toolsDesigning digital logic circuits, working on HDL coding and simulation
Industry UsageFoundries, semiconductor companies, integrated circuit design firmsSemiconductor companies, integrated circuit design firms, tech companies

Physical Design Engineer Interns focus on translating digital logic designs into physical layouts for chips, working closely with EDA tools. Digital Design Engineer Interns concentrate on creating and simulating digital logic circuits using hardware description languages. Both roles are essential in chip development but differ in their specific tasks and focus areas.

What job categories do people searching Physical Design Engineer Intern jobs in Roxbury, MA look for?

The top searched job categories for Physical Design Engineer Intern jobs in Roxbury, MA are:

What cities near Roxbury, MA are hiring for Physical Design Engineer Intern jobs?

Cities near Roxbury, MA with the most Physical Design Engineer Intern job openings:

Physical Design Engineer Intern jobs near you
Infographic showing various Physical Design Engineer Intern job openings in Roxbury, MA as of August 2026, with employment types broken down into 1% As Needed, 78% Full Time, 16% Part Time, 4% Contract, and 1% Nights. Highlights an 95% Physical, 2% Hybrid, and 3% Remote job distribution, with an average salary of $43,599 per year, or $21 per hour.

Advanced ASIC RTL to Netlist Physical Design Lead (Teradyne, North Reading, MA)

Teradyne

Reading, MA • On-site

$192.30 - $307.60/hr

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Medical, Dental, Vision, Life, Retirement, PTO

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Job description

Advanced ASIC RTL to Netlist Physical Design Lead (Teradyne, North Reading, MA)

Location: North Reading, MA, US

We are the global test and automation specialists, powering next-generation technologies through sophisticated solutions. Behind every electronic device you use, Teradyne's test technology ensures your device works right the first time, every time! Our portfolio of automation solutions help manufacturers to develop and deliver products quickly, efficiently and cost-effectively. Together, Teradyne companies deliver manufacturing automation across industries and applications around the world!

Opportunity Overview

Teradyne is seeking an experienced Physical Design Lead to join our Silicon Technology Engineering (STE) organization within the Digital ASIC Group. This team develops advanced-node, large-scale mixed-signal ASICs that are foundational to Teradyne’s next-generation SoC and memory test platforms.

In this highly visible technical leadership role, you will own RTL-to-GDSII execution for complex ASICs, working closely with digital and analog designers, product architects, and chip leads. You will guide physical design architecture, mentor engineers, and play a critical role in delivering high-quality, first-pass silicon at advanced process nodes.

What You’ll Do
  • Lead and mentor a team of physical design engineers across the full project lifecycle
  • Lead high-level physical design planning and define PD architecture in collaboration with chip and system architects
  • Develop and own chip floorplans, timing budgets, power estimates, and pin planning
  • Partner with design teams to develop high-quality SDC constraints
  • Drive RTL-to-netlist activities including synthesis, logical equivalence checking (LEC), clock domain crossing checks (CDC), and static timing analysis (STA)
  • Support hands‑on place‑and‑route (P&R) for critical and high‑speed blocks
  • Collaborate with a backend physical design house to support P&R execution, debug flow or implementation issues, and meet schedule and quality goals
  • Integrate complex IP such as PCIe, DDR5/DDR6, UFS, and SerDes
  • Ensure robust signoff closure including DRC/LVS and EM/IR analysis
  • Develop, enhance, and maintain physical design tool flows and automation
All About You
  • 10+ years of hands‑on ASIC physical design experience, including leadership of large or complex PD projects
  • Proven experience at advanced technology nodes (16nm and below)
  • Deep expertise in RTL-to-GDSII flows and timing closure
  • Strong understanding of STA, constraints development, and signoff methodologies
  • Experience integrating high-speed and complex IP (e.g., PCIe, DDR5/DDR6, UFS, SerDes)
  • Proficiency with industry-standard EDA tools (Cadence preferred)
  • Strong scripting and automation skills using Tcl, Python, and/or Make
  • Ability to lead technically, communicate clearly, and collaborate across disciplines
  • BS or MS in Electrical Engineering (or equivalent practical experience)
Why Teradyne
  • Work on cutting‑edge silicon that directly impacts the semiconductor ecosystem
  • High technical ownership and visibility
  • Collaborative, engineering‑driven culture
  • Competitive compensation, benefits, and career growth opportunities

Compensation: The base salary range for this role is $192,300 to $307,600. This range is a good faith estimate, and the amount of base salary will correspond with experience and skill set. This range can also fluctuate depending on demand and location.

Incentive Plan: This job is eligible for discretionary bonus(es) based on financial performance.

Benefits: Teradyne offers a variety of robust health and well‑being benefit programs, including medical, dental, vision, Flexible Spending Accounts, retirement savings plans, life and disability insurance, paid vacation & holidays, tuition assistance programs, and more. Please click here to see details.

We are an equal‑opportunity employer and value diversity at our company. We do not discriminate on the basis of race, religion, color, national origin, sex, gender, gender expression, sexual orientation, age, marital status, veteran status, or disability status. We will ensure that individuals with disabilities are provided reasonable accommodation to participate in the job application or interview process, to perform crucial job functions, and to receive other benefits and privileges of employment.

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