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How much do physical design engineer intern jobs pay per hour?

As of Jun 9, 2026, the average hourly pay for physical design engineer intern in Raleigh, NC is $18.78, according to ZipRecruiter salary data. Most workers in this role earn between $15.67 and $20.34 per hour, depending on experience, location, and employer.

What are the key skills and qualifications needed to thrive as a Physical Design Engineer Intern, and why are they important?

To thrive as a Physical Design Engineer Intern, you generally need a solid background in electrical engineering, digital circuit design, and semiconductor fundamentals, often supported by ongoing university studies in a related field. Familiarity with industry-standard EDA tools such as Cadence, Synopsys, or Mentor Graphics, as well as scripting languages like TCL or Python, is highly valuable. Attention to detail, problem-solving abilities, and effective teamwork are crucial soft skills for excelling in this role. These skills and qualifications are important because they ensure accurate chip layouts, efficient workflows, and successful collaboration within complex engineering teams.

What types of projects and tasks can a Physical Design Engineer Intern expect to work on during their internship?

As a Physical Design Engineer Intern, you will typically be involved in supporting the design and verification of integrated circuits at the physical level. Common tasks include assisting with floorplanning, placement and routing, timing analysis, and running design rule checks using industry-standard EDA tools. You may also participate in team meetings, collaborate with senior engineers, and help resolve issues related to power, performance, and area optimization. These hands-on experiences are designed to help you build practical skills and gain a deeper understanding of the physical design flow in VLSI chip development.

What does a Physical Design Engineer Intern do?

A Physical Design Engineer Intern assists in the process of transforming a circuit design (RTL) into a real, manufacturable layout for semiconductor chips. They work on tasks such as floorplanning, placement, routing, timing analysis, and verifying that the chip design meets all physical and electrical requirements. Interns typically use electronic design automation (EDA) tools to perform these tasks and collaborate with experienced engineers. Their work is crucial in ensuring that chips are both functional and manufacturable at scale.

What is the difference between Physical Design Engineer Intern vs Digital Design Engineer Intern?

AspectPhysical Design Engineer InternDigital Design Engineer Intern
Required CredentialsTypically pursuing or holding a degree in Electrical Engineering or Computer EngineeringTypically pursuing or holding a degree in Electrical Engineering or Computer Engineering
Work EnvironmentDesigning and implementing physical chip layouts, working with EDA toolsDesigning digital logic circuits, working on HDL coding and simulation
Industry UsageFoundries, semiconductor companies, integrated circuit design firmsSemiconductor companies, integrated circuit design firms, tech companies

Physical Design Engineer Interns focus on translating digital logic designs into physical layouts for chips, working closely with EDA tools. Digital Design Engineer Interns concentrate on creating and simulating digital logic circuits using hardware description languages. Both roles are essential in chip development but differ in their specific tasks and focus areas.

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Physical Design Engineer Intern jobs near you
Infographic showing various Physical Design Engineer Intern job openings in Raleigh, NC as of June 2026, with employment types broken down into 99% Full Time, and 1% Part Time. Highlights an 87% Physical, 5% Hybrid, and 8% Remote job distribution, with an average salary of $39,053 per year, or $18.8 per hour.
Senior Principal Engineer, Physical Design

Senior Principal Engineer, Physical Design

Marvell Technology, Inc.

Morrisville, NC • On-site

$117K - $161K/yr

Full-time

Medical, Retirement, PTO

Posted yesterday

Job description

About Marvell
Marvell's semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities.
At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.
Your Team, Your Impact
Built on decades of expertise and execution, Marvell's custom Processor/ASIC solution offers a differentiated approach with a best-in-class portfolio of data infrastructure intellectual property (IP) and a wide array of flexible business models. In this unique role, you'll have the opportunity to work on both the physical design and methodology for future designs of our next-generation, high-performance processor chips in a leading-edge CMOS process technology, targeted at server, and networking applications.
What You Can Expect
As a senior leader in the central physical design team, you will:
  • Shape the long-term vision for physical design capabilities and infrastructure in alignment with company-wide technology strategy
  • Lead RTL-to-GDSII implementation for multiple SoC programs, overseeing synthesis, floorplanning, power grid design, place and route, clock tree synthesis, timing closure, power/signal integrity signoff, and physical verification (DRC/LVS)
  • Provide strategic leadership and technical direction to physical design teams, ensuring successful and timely tapeouts of complex, high-performance SoCs
  • Mentor and develop engineering talent, fostering a culture of innovation, collaboration, and continuous improvement
  • Oversee team structure, hiring, performance management, and career development to build and retain a high-performing physical design organization
  • Drive cross-functional collaboration with design teams to influence design decisions and ensure successful project execution
  • Navigate and resolve cross-functional conflicts effectively, fostering alignment and maintaining momentum across diverse teams
  • Drive the development and adoption of next-generation physical design methodologies, flows, and automation to improve productivity and design quality

What We're Looking For
  • Bachelor's degree in Computer Science, Electrical Engineering or related fields and 15+ years of related professional experience or Master's degree in Computer Science, Electrical Engineering or related fields with 10-12 years of experience or PhD in Computer Science, Electrical Engineering or related fields with 8-10 years of experience or equivalent professional experience in lieu of a formal degree
  • 15+ years of progressive experience in back-end physical design and verification, including significant leadership roles
  • Proven track record of leading and scaling physical design teams, managing complex SoC projects, and delivering high-quality tapeouts under aggressive schedules
  • Deep expertise in hierarchical physical design strategies, methodologies, and advanced process node challenges
  • In-depth understanding of current design technologies used in major foundries
  • Strong understanding of ASIC design flow, RTL integration, synthesis, and timing closure
  • In-depth knowledge of modern EDA tools and flows
  • Proficient in automation and scripting using Makefile, Tcl, Python, or Perl to enhance design efficiency and flow robustness
  • Strong communication and collaboration skills, with the ability to influence cross-functional teams and executive stakeholders
  • Experience in developing and deploying advanced physical design methodologies and flows
  • Strong knowledge on static timing analysis (PrimeTime, Tempus), EM/IR-Drop/crosstalk analysis (PTSI, Voltus, Redhawk, PrimeRail), extraction (Quantus, StarRC), formal or physical verification (Formality, Verplex, Calibre, Hercules) a plus
  • Familiarity with AI/ML-driven optimization in physical design tools is a plus

Expected Base Pay Range (USD)
170,800 - 252,750, $ per annum
The successful candidate's starting base pay will be determined based on job-related skills, experience, qualifications, work location and market conditions. The expected base pay range for this role may be modified based on market conditions.
Additional Compensation and Benefit Elements
At Marvell, we offer a total compensation package with a base, bonus and equity.Health and financial wellbeing are part of the package. That means flexible time off, 401k, plus a year-end shutdown, floating holidays, paid time off to volunteer. Have a question about our benefits packages - health or financial? Ask your recruiter during the interview process.
All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.
Any applicant who requires a reasonable accommodation during the selection process should contact Marvell HR Helpdesk at TAOps@marvell.com.
Interview Integrity
As part of our commitment to fair and authentic hiring practices, we ask that candidates do not use AI tools (e.g., transcription apps, real-time answer generators like ChatGPT, CoPilot, or note-taking bots) during interviews.
Our interviews are designed to assess your personal experience, thought process, and communication skills in real-time. If a candidate uses such tools during an interview, they will be disqualified from the hiring process.
This position may require access to technology and/or software subject to U.S. export control laws and regulations, including the Export Administration Regulations (EAR). As such, applicants must be eligible to access export-controlled information as defined under applicable law. Marvell may be required to obtain export licensing approval from the U.S. Department of Commerce and/or the U.S. Department of State. Except for U.S. citizens, lawful permanent residents, or protected individuals as defined by 8 U.S.C. 1324b(a)(3), all applicants may be subject to an export license review process prior to employment.
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