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Physical Design Engineer Intern Jobs in El Segundo, CA

Apple

IC Package Design Engineer

Los Angeles, CA · On-site

$146K/yr

Description As a Package design engineer, you will lead advanced package architecture, drive next ... Proven experience in IC package physical design using Cadence Allegro or Mentor Xpedition platforms ...

Apple

IC Package Design Engineer

Los Angeles, CA

$122K - $214K/yr

Description As a Package design engineer, you will lead advanced package architecture, drive next ... Proven experience in IC package physical design using Cadence Allegro or Mentor Xpedition platforms ...

Apple

IC Package Design Engineer

Los Angeles, CA

$122K - $214K/yr

Description As a Package design engineer, you will lead advanced package architecture, drive next ... Proven experience in IC package physical design using Cadence Allegro or Mentor Xpedition platforms ...

Apple

IC Package Design Engineer

Los Angeles, CA

$122K - $214K/yr

Description As a Package design engineer, you will lead advanced package architecture, drive next ... Proven experience in IC package physical design using Cadence Allegro or Mentor Xpedition platforms ...

ACCO Engineered Systems

Design Engineer

Pasadena, CA · On-site

Detailed physical design experience in the development of mechanical general arrangements, piping ... Prior intern experience with mechanical contractor and/or engineering consultant Desired : * 2-5 ...

ACCO Engineered Systems

Design Engineer

Pasadena, CA · On-site

Detailed physical design experience in the development of mechanical general arrangements, piping ... Prior intern experience with mechanical contractor and/or engineering consultant Desired : * 2-5 ...

Apple Inc.

IC Package Design Engineer

Los Angeles, CA · On-site

$171.60 - $302.20/hr

Description As a Package design engineer, you will lead advanced package architecture, drive ... Perform physical layout of package substrates for diverse silicon, including System‑on‑Chip ...

Keltia Design

WH DE Linkedin-Apr 2024

Los Angeles, CA · On-site

... Design Engineer with our client in Los Angeles area in CA who is working on an Airbus A330 Freighter Aircraft. Developing and maintaining Wire Harness physical design and installation • Performing ...

Voxelcloud

Data Engineer Intern

Los Angeles, CA

$123K - $148K/yr

Reporting to Data Team Lead, the Data Engineer intern will participate in the acquisition and ... Identify, design, and implement internal process improvements: automating data QA, optimizing data ...

Centerfield

Software Engineer Intern

Los Angeles, CA · On-site

As a Software Engineering intern at Centerfield, you'll work directly with our Engineering team ... Understanding of SQL and relational database concepts, including database design and writing ...

Centerfield

Software Engineer Intern

Los Angeles, CA · On-site

As a Software Engineering intern at Centerfield, you'll work directly with our Engineering team ... Understanding of SQL and relational database concepts, including database design and writing ...

Centerfield

Software Engineer Intern

Los Angeles, CA · Hybrid

As a Software Engineering intern at Centerfield, you'll work directly with our Engineering team ... Understanding of SQL and relational database concepts, including database design and writing ...

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All JobsPhysical Design Engineer Intern JobsPhysical Design Engineer Intern Jobs in El Segundo, CA

Physical Design Engineer Intern information

See El Segundo, CA salary details

$11

$20

$31

How much do physical design engineer intern jobs pay per hour?

As of Aug 19, 2026, the average hourly pay for physical design engineer intern in El Segundo, CA is $20.57, according to ZipRecruiter salary data. Most workers in this role earn between $17.16 and $22.26 per hour, depending on experience, location, and employer.

What does a physical design engineer intern do?

A Physical Design Engineer Intern assists in the process of transforming a circuit design (RTL) into a real, manufacturable layout for semiconductor chips. They work on tasks such as floorplanning, placement, routing, timing analysis, and verifying that the chip design meets all physical and electrical requirements. Interns typically use electronic design automation (EDA) tools to perform these tasks and collaborate with experienced engineers. Their work is crucial in ensuring that chips are both functional and manufacturable at scale.

What skills and qualifications are needed to thrive as a physical design engineer intern?

To thrive as a Physical Design Engineer Intern, you generally need a solid background in electrical engineering, digital circuit design, and semiconductor fundamentals, often supported by ongoing university studies in a related field. Familiarity with industry-standard EDA tools such as Cadence, Synopsys, or Mentor Graphics, as well as scripting languages like TCL or Python, is highly valuable. Attention to detail, problem-solving abilities, and effective teamwork are crucial soft skills for excelling in this role. These skills and qualifications are important because they ensure accurate chip layouts, efficient workflows, and successful collaboration within complex engineering teams.

What types of projects and tasks can a physical design engineer intern expect to work on during their internship?

As a Physical Design Engineer Intern, you will typically be involved in supporting the design and verification of integrated circuits at the physical level. Common tasks include assisting with floorplanning, placement and routing, timing analysis, and running design rule checks using industry-standard EDA tools. You may also participate in team meetings, collaborate with senior engineers, and help resolve issues related to power, performance, and area optimization. These hands-on experiences are designed to help you build practical skills and gain a deeper understanding of the physical design flow in VLSI chip development.

What is the difference between Physical Design Engineer Intern vs Digital Design Engineer Intern?

AspectPhysical Design Engineer InternDigital Design Engineer Intern
Required CredentialsTypically pursuing or holding a degree in Electrical Engineering or Computer EngineeringTypically pursuing or holding a degree in Electrical Engineering or Computer Engineering
Work EnvironmentDesigning and implementing physical chip layouts, working with EDA toolsDesigning digital logic circuits, working on HDL coding and simulation
Industry UsageFoundries, semiconductor companies, integrated circuit design firmsSemiconductor companies, integrated circuit design firms, tech companies

Physical Design Engineer Interns focus on translating digital logic designs into physical layouts for chips, working closely with EDA tools. Digital Design Engineer Interns concentrate on creating and simulating digital logic circuits using hardware description languages. Both roles are essential in chip development but differ in their specific tasks and focus areas.

What are popular job titles related to Physical Design Engineer Intern jobs in El Segundo, CA?

For Physical Design Engineer Intern jobs in El Segundo, CA, the most frequently searched job titles are:

What job categories do people searching Physical Design Engineer Intern jobs in El Segundo, CA look for?

The top searched job categories for Physical Design Engineer Intern jobs in El Segundo, CA are:

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Cities near El Segundo, CA with the most Physical Design Engineer Intern job openings:

Physical Design Engineer Intern jobs near you
Infographic showing various Physical Design Engineer Intern job openings in El Segundo, CA as of August 2026, with employment types broken down into 1% As Needed, 70% Full Time, 23% Part Time, 2% Temporary, 2% Contract, and 2% Nights. Highlights an 97% Physical, 1% Hybrid, and 2% Remote job distribution, with an average salary of $42,792 per year, or $20.6 per hour.

Principal ASIC Physical Design Engineer

K2 Space

Los Angeles, CA

$190K - $280K/yr

Full-time

Re-posted 24 days ago

Job description

K2 is building the largest and highest-power satellites ever flown, unlocking performance levels previously out of reach across every orbit. Backed by $450M from leading investors including Altimeter Capital, Redpoint Ventures, T. Rowe Price, Lightspeed Venture Partners, Alpine Space Ventures, and others – with an additional $500M in signed contracts across commercial and US government customers – we're mass-producing the highest-power satellite platforms ever built for missions from LEO to deep space.

The rise of heavy-lift launch vehicles is shifting the industry from an era of mass constraint to one of mass abundance, and we believe this new era demands a fundamentally different class of spacecraft. Engineered to survive the harshest radiation environments and to fully capitalize on today's and tomorrow's massive rockets, K2 satellites deliver unmatched capability at constellation scale and across multiple orbits.

With multiple launches planned through 2026 and 2027, we're Building Bigger to develop the solar system and become a Kardashev Type II (K2) civilization. If you are a motivated individual who thrives in a fast-paced environment and you're excited about contributing to the success of a groundbreaking Series C space startup, we'd love for you to apply.

The Role

We are looking for a Principal ASIC Physical Design Engineer to lead the implementation of complex SoCs for next-generation satellite and space systems. You will own the full physical design flow—from RTL handoff to GDSII—and collaborate closely with architecture, RTL design, DFT, and packaging teams. This role also involves managing external physical design partners, driving tool and flow decisions, and ensuring first-pass silicon success in advanced FinFET technologies. You'll be a key contributor in achieving timing closure, optimizing PPA, and supporting design integration with external partners. You will be part of a collaborative design team developing state-of-the-art mixed-signal SoCs to be hosted on some of the largest, most powerful, rapidly designed and rapidly manufactured satellites ever deployed in space. In your first 6 months, you will develop and implement new SoC sub-systems for satellite communications and beyond. In your first two years, you will have contributed to developing cutting-edge SoCs that will fly in space.

Responsibilities

  • Own the complete RTL-to-GDSII flow: synthesis, floorplanning, place & route, clock tree synthesis (CTS), static timing analysis (STA), physical verification (DRC/LVS), and sign-off.
  • Develop and maintain physical design methodologies, scripts, and automation to optimize performance, power, and area (PPA).
  • Collaborate with front-end and verification teams to ensure clean handoffs, timing closure, and efficient design iteration.
  • Drive timing closure across multiple voltage and process corners, including sign-off with foundry-qualified tools.
  • Partner with package, SI/PI, and test teams for package-aware floorplanning and chip-to-board integration.
  • Manage and technically guide external physical design partners and service vendors, ensuring alignment on milestones, deliverables, and quality standards.
  • Work with EDA vendors to debug and optimize tool flows, and evaluate new methodologies.
  • Support chip bring-up and debug through close collaboration with post-silicon and test teams.
  • Support your product through production and spaceflight.

Required Qualifications

  • Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or related field.
  • 10+ years of experience in ASIC physical design for high-performance SoCs.
  • Proven end-to-end expertise in RTL-to-GDSII flows using industry tools (Synopsys, Cadence, or Siemens).
  • Strong hands-on experience with timing closure, IR drop analysis, and ECO implementation.
  • Deep understanding of physical design constraints for multi-clock, multi-voltage, and hierarchical SoCs.
  • Experience with advanced FinFET process nodes.
  • Prior experience managing or coordinating offshore/outsourced PD teams or vendors.
  • Familiarity with DFT integration, STA sign-off, and power domain implementation (UPF/CPF).
  • Excellent communication, leadership, and cross-functional collaboration skills.
  • Act as technical leader and subject-matter expert helping to teach, grow, and mentor others in the team.

Preferred Qualifications

  • Exposure to radiation-hardened or space-qualified ASICs.
  • Experience with chip-package co-design or advanced packaging (2.5D/3D).
  • Familiarity with physical design service vendor management or offshore collaboration.
  • Experience driving tapeouts through TSMC.
  • Experience with Gate-All-Around technologies.
  • Experience working in cross-functional, geographically distributed teams.

Compensation and Benefits:

  • Base salary range for this role is $190,000 – $280,000 + equity in the company
  • Salary will be based on several factors including, but not limited to: knowledge and skills, education, and experience level
  • Comprehensive benefits package including paid time off, medical/dental/vision/ coverage, life insurance, paid parental leave, and many other perks

If you don't meet 100% of the preferred skills and experience, we encourage you to still apply! Building a spacecraft unlike any other requires a team unlike any other and non-traditional career twists and turns are encouraged!

If you need a reasonable accommodation as part of your application for employment or interviews with us, please let us know.

Export Compliance

As defined in the ITAR, "U.S. Persons" include U.S. citizens, lawful permanent residents (i.e., Green Card holders), and certain protected individuals (e.g., refugees/asylees, American Samoans). Please consult with a knowledgeable advisor if you are unsure whether you are a "U.S. Person."

The person hired for this role will have access to information and items controlled by U.S. export control regulations, including the export control regulations outlined in the International Traffic in Arms Regulation (ITAR). The person hired for this role must therefore either be a "U.S. person" as defined by 22 C.F.R. § 120.15 or otherwise eligible for a federally issued export control license.

Equal Opportunity

K2 Space is an Equal Opportunity Employer; employment with K2 Space is governed on the basis of merit, competence and qualifications and will not be influenced in any manner by race, color, religion, gender, national origin/ethnicity, veteran status, disability status, age, sexual orientation, gender identity, marital status, mental or physical disability or any other legally protected status.

K2 Space logo

About K2 Space

Sourced by ZipRecruiter

Industry

Guided missile and space vehicle manufacturing

Company size

11 - 50 Employees

Headquarters location

Los Angeles, CA, US

Year founded

2022

View All K2 Space Jobs