Our solutions are designed to not only meet the current demands of the digital landscape but to ... PCIe software engineers write the code that manages high speed communication between hardware ...
Our solutions are designed to not only meet the current demands of the digital landscape but to ... PCIe software engineers write the code that manages high speed communication between hardware ...
PCIe Software Engineer
Nashua, NH · On-site
Our solutions are designed to not only meet the current demands of the digital landscape but to ... PCIe software engineers write the code that manages high speed communication between hardware ...
PCIe Software Engineer
Nashua, NH · On-site
Our solutions are designed to not only meet the current demands of the digital landscape but to ... PCIe software engineers write the code that manages high speed communication between hardware ...
PCIe Software Engineer
Austin, TX · On-site
Our solutions are designed to not only meet the current demands of the digital landscape but to ... PCIe software engineers write the code that manages high speed communication between hardware ...
PCIe Software Engineer
Austin, TX · On-site
Our solutions are designed to not only meet the current demands of the digital landscape but to ... PCIe software engineers write the code that manages high speed communication between hardware ...
PCIe Software Engineer
Nashua, NH · On-site
Our solutions are designed to not only meet the current demands of the digital landscape but to ... PCIe software engineers write the code that manages high speed communication between hardware ...
PCIe Software Engineer
Nashua, NH · On-site
Our solutions are designed to not only meet the current demands of the digital landscape but to ... PCIe software engineers write the code that manages high speed communication between hardware ...
PCIe Software Engineer
Austin, TX · On-site
Our solutions are designed to not only meet the current demands of the digital landscape but to ... PCIe software engineers write the code that manages high speed communication between hardware ...
PCIe Software Engineer
Austin, TX · On-site
Our solutions are designed to not only meet the current demands of the digital landscape but to ... PCIe software engineers write the code that manages high speed communication between hardware ...
PCIe Software Engineer
Austin, TX · On-site
Our solutions are designed to not only meet the current demands of the digital landscape but to ... PCIe software engineers write the code that manages high speed communication between hardware ...
PCIe Software Engineer
Austin, TX · On-site
Our solutions are designed to not only meet the current demands of the digital landscape but to ... PCIe software engineers write the code that manages high speed communication between hardware ...
PCIe Software Engineer
Santa Clara, CA · On-site
$123K - $191K/yr
Our solutions are designed to not only meet the current demands of the digital landscape but to ... PCIe software engineers write the code that manages high speed communication between hardware ...
PCIe Software Engineer
Santa Clara, CA · On-site
$123K - $191K/yr
Our solutions are designed to not only meet the current demands of the digital landscape but to ... PCIe software engineers write the code that manages high speed communication between hardware ...
Principal PCIe Subsystem RTL lead
San Jose, CA · On-site
$200 - $250/hr
Hands-on experience integrating PCIe hard IP (controller and/or SerDes PHY) into production SoC or chiplet designs, including wrapper RTL, reset sequencing, and PnR constraints. * Background in SR ...
Principal PCIe Subsystem RTL lead
San Jose, CA · On-site
$200 - $250/hr
Hands-on experience integrating PCIe hard IP (controller and/or SerDes PHY) into production SoC or chiplet designs, including wrapper RTL, reset sequencing, and PnR constraints. * Background in SR ...
Principal PCIe Subsystem RTL lead
San Jose, CA · On-site
$159K - $164K/yr
Hands-on experience integrating PCIe hard IP (controller and/or SerDes PHY) into production SoC or chiplet designs, including wrapper RTL, reset sequencing, and PnR constraints. * Background in SR ...
Principal PCIe Subsystem RTL lead
San Jose, CA · On-site
$159K - $164K/yr
Hands-on experience integrating PCIe hard IP (controller and/or SerDes PHY) into production SoC or chiplet designs, including wrapper RTL, reset sequencing, and PnR constraints. * Background in SR ...
PCIe Software Engineer
Santa Clara, CA · On-site
$123K - $191K/yr
Our solutions are designed to not only meet the current demands of the digital landscape but to ... PCIe software engineers write the code that manages high speed communication between hardware ...
PCIe Software Engineer
Santa Clara, CA · On-site
$123K - $191K/yr
Our solutions are designed to not only meet the current demands of the digital landscape but to ... PCIe software engineers write the code that manages high speed communication between hardware ...
TPU PCIe RTL Design Engineer
Sunnyvale, CA · On-site
Beyond designing high-performance PCIe subsystems, you will build the foundational SoC infrastructure-including clocking, reset, error handling, and chip management-that powers our silicon. Your ...
TPU PCIe RTL Design Engineer
Sunnyvale, CA · On-site
Beyond designing high-performance PCIe subsystems, you will build the foundational SoC infrastructure-including clocking, reset, error handling, and chip management-that powers our silicon. Your ...
PCIe ASIC Design Engineer
San Jose, CA · On-site +1
Own end-to-end integration of PCIe IP into complex ASIC designs. * Collaborate with IP vendors, architecture, verification, physical design, and software teams to deliver robust PCIe subsystems.
PCIe ASIC Design Engineer
San Jose, CA · On-site +1
Own end-to-end integration of PCIe IP into complex ASIC designs. * Collaborate with IP vendors, architecture, verification, physical design, and software teams to deliver robust PCIe subsystems.
PCIe Senior/Lead Software Engineer
Austin, TX · On-site
Our solutions are designed to not only meet the current demands of the digital landscape but to ... PCIe software engineers write the code that manages high speed communication between hardware ...
PCIe Senior/Lead Software Engineer
Austin, TX · On-site
Our solutions are designed to not only meet the current demands of the digital landscape but to ... PCIe software engineers write the code that manages high speed communication between hardware ...
PCIe Senior/Lead Software Engineer
Nashua, NH · On-site
Our solutions are designed to not only meet the current demands of the digital landscape but to ... PCIe software engineers write the code that manages high speed communication between hardware ...
PCIe Senior/Lead Software Engineer
Nashua, NH · On-site
Our solutions are designed to not only meet the current demands of the digital landscape but to ... PCIe software engineers write the code that manages high speed communication between hardware ...
PCIe QA Engineer
San Jose, CA · On-site
$100 - $125/hr
The candidate should have an understanding of PCIe protocol - Gen3 & above, a system-level understanding of PCI-E-based designs, and hands-on experience in Python programming. Good understanding of ...
PCIe QA Engineer
San Jose, CA · On-site
$100 - $125/hr
The candidate should have an understanding of PCIe protocol - Gen3 & above, a system-level understanding of PCI-E-based designs, and hands-on experience in Python programming. Good understanding of ...
PCIe Senior/Lead Software Engineer
Austin, TX · On-site
Our solutions are designed to not only meet the current demands of the digital landscape but to ... PCIe software engineers write the code that manages high speed communication between hardware ...
PCIe Senior/Lead Software Engineer
Austin, TX · On-site
Our solutions are designed to not only meet the current demands of the digital landscape but to ... PCIe software engineers write the code that manages high speed communication between hardware ...
PCIe ASIC Design Engineer
Austin, TX · On-site +1
Own end-to-end integration of PCIe IP into complex ASIC designs. * Collaborate with IP vendors, architecture, verification, physical design, and software teams to deliver robust PCIe subsystems.
PCIe ASIC Design Engineer
Austin, TX · On-site +1
Own end-to-end integration of PCIe IP into complex ASIC designs. * Collaborate with IP vendors, architecture, verification, physical design, and software teams to deliver robust PCIe subsystems.
PCIe ASIC Design Engineer
Austin, TX · On-site
Own end-to-end integration of PCIe IP into complex ASIC designs. * Collaborate with IP vendors, architecture, verification, physical design, and software teams to deliver robust PCIe subsystems.
PCIe ASIC Design Engineer
Austin, TX · On-site
Own end-to-end integration of PCIe IP into complex ASIC designs. * Collaborate with IP vendors, architecture, verification, physical design, and software teams to deliver robust PCIe subsystems.
PCIe Senior/Lead Software Engineer
Santa Clara, CA · On-site
$140K - $210K/yr
Our solutions are designed to not only meet the current demands of the digital landscape but to ... PCIe software engineers write the code that manages high speed communication between hardware ...
PCIe Senior/Lead Software Engineer
Santa Clara, CA · On-site
$140K - $210K/yr
Our solutions are designed to not only meet the current demands of the digital landscape but to ... PCIe software engineers write the code that manages high speed communication between hardware ...
Design Verification Engineer (Sunnyvale)
Sunnyvale, CA · On-site
$119K - $258K/yr
Verify UCIe , Ethernet MAC & PCS , and PCIe designs * Support PCIe Root of Trust verification, including Rambus IP * Create verification plans, tests, assertions, and coverage * Debug issues and ...
Design Verification Engineer (Sunnyvale)
Sunnyvale, CA · On-site
$119K - $258K/yr
Verify UCIe , Ethernet MAC & PCS , and PCIe designs * Support PCIe Root of Trust verification, including Rambus IP * Create verification plans, tests, assertions, and coverage * Debug issues and ...
Pcie Designer information
See salary details
$21.5K - $29.7K
9% of jobs
$29.7K - $38K
1% of jobs
$44.2K is the 25th percentile. Wages below this are outliers.
$38K - $46.2K
20% of jobs
$46.2K - $54.4K
12% of jobs
The median wage is $60.4K / yr.
$54.4K - $62.6K
12% of jobs
$62.6K - $70.9K
17% of jobs
$76.2K is the 75th percentile. Wages above this are outliers.
$70.9K - $79.1K
7% of jobs
$79.1K - $87.3K
4% of jobs
$87.3K - $95.5K
7% of jobs
$95.5K - $103.8K
4% of jobs
$103.8K - $112K
6% of jobs
$21.5K
$65.4K
$112K
How much do pcie designer jobs pay per year?
What are popular job titles related to Pcie Designer jobs?
For Pcie Designer jobs, the most frequently searched job titles are:

PCIe Software Engineer
Nashua, NH
Full-time
Re-posted 3 days ago
Job description
Company Description
Arista Networks is an industry leader in data-driven, client-to-cloud networking for large data center, campus and routing environments. What sets us apart is our relentless pursuit of innovation. We leverage the latest advancements in cloud computing, artificial intelligence, and software-defined networking to provide our clients with a competitive edge in an increasingly interconnected world. Our solutions are designed to not only meet the current demands of the digital landscape but to also anticipate and adapt to future challenges.
At Arista we value the diversity of thought and perspectives that each employee brings to the table. We believe that fostering an inclusive environment, where individuals from various backgrounds and experiences feel welcome, is essential for driving creativity and innovation.
Our commitment to excellence has earned us several prestigious awards, such as Best Engineering Team, Best Company for Diversity, Compensation, and Work-Life Balance. At Arista, we take pride in our track record of success and strive to maintain the highest standards of quality and performance in everything we do.
Job Description
Who You'll Work With
Operating right where hardware meets software, the Platform team builds the foundation for our networking ASICs and supporting infrastructure. PCIe software engineers write the code that manages high speed communication between hardware components in our switches. We work with hardware, diagnostics, and software engineers to maximize bandwidth and improve reliability on the PCIe links.
What You'll Do
As part of this team, you’ll work on projects like:
- Bringing up pcie links on new hardware designs
- Tuning pcie parameters on root ports, bridges, and end points
- Modifying the linux pci drivers and virtual memory allocation
- Using AER and DPC to improve error visibility and resiliency
- Developing userspace software that mediate between networking ASICs, FPGAs, and PCIe bridges.
- Measuring hardware read and write performance
- Develop automated tests using C, C++ and Python to validate your features.
Qualifications
- Strong engineering and Computer Science fundamentals.
- 3+ years fluency in C or C++. Python experience an added bonus.
- Solid understanding of PCIe hardware and software drivers
- PCIe state machine, ltssm, tlp, credit flow control knowledge a plus
- Experience with PCIe switches
- Significant hands-on experience diagnosing problems, troubleshooting issues, and fixing bugs in low-level firmware
If you’re passionate about performance optimizations and enjoy working at the hardware/software boundary, the Platform team is a perfect choice!
Additional Information
Arista Networks is an equal opportunity employer. Arista makes all hiring and employment-related decisions in a non-discriminatory manner without regard to race, color, religion, sex, sexual orientation, gender identity, national origin or any other factor determined to be unlawful under applicable federal, state, or law law. All your information will be kept confidential according to EEO guidelines.
About Arista NDR
Sourced by ZipRecruiter
Industry
Network security
Company size
51 - 200 Employees
Headquarters location
Santa Clara, CA, US
Year founded
2014