You will partner closely with development, process, product engineering, and manufacturing teams across sites to ensure our test strategy scales with increasingly complex device portfolios. What You ...
You will partner closely with development, process, product engineering, and manufacturing teams across sites to ensure our test strategy scales with increasingly complex device portfolios. What You ...
Staff/Principal ATE Test Engineer
Torrance, CA · On-site
$160K - $200K/yr
This role is focused primarily on semiconductor test engineering, spanning DFT collaboration, characterization support, wafer probe, final test, hardware development, production ramp, and ...
Staff/Principal ATE Test Engineer
Torrance, CA · On-site
$160K - $200K/yr
This role is focused primarily on semiconductor test engineering, spanning DFT collaboration, characterization support, wafer probe, final test, hardware development, production ramp, and ...
You will partner closely with development, process, product engineering, and manufacturing teams across sites to ensure our test strategy scales with increasingly complex device portfolios. What You ...
You will partner closely with development, process, product engineering, and manufacturing teams across sites to ensure our test strategy scales with increasingly complex device portfolios. What You ...
About Marvell Marvell's semiconductor solutions are the essential building blocks of the data ... As a Senior Level Test Engineering Manager, you will define and drive test engineering strategy ...
About Marvell Marvell's semiconductor solutions are the essential building blocks of the data ... As a Senior Level Test Engineering Manager, you will define and drive test engineering strategy ...
ATE Test Engineer IRC295876
Denver, CO · On-site +1
$100K - $120K/yr
Requirements Minimum 5 years of experience in test engineering or related semiconductor testing roles. Hands-on experience with Advantest V93000 SoC test systems. Experience supporting SoC testing ...
ATE Test Engineer IRC295876
Denver, CO · On-site +1
$100K - $120K/yr
Requirements Minimum 5 years of experience in test engineering or related semiconductor testing roles. Hands-on experience with Advantest V93000 SoC test systems. Experience supporting SoC testing ...
Test Engineering Intern
San Jose, CA · On-site
$31.25 - $41.50/hr
As a Test Engineering Intern , you will work alongside experienced test engineers to support the ... Exposure to semiconductor devices, VLSI, or mixed-signal circuit design through coursework or ...
Test Engineering Intern
San Jose, CA · On-site
$31.25 - $41.50/hr
As a Test Engineering Intern , you will work alongside experienced test engineers to support the ... Exposure to semiconductor devices, VLSI, or mixed-signal circuit design through coursework or ...
Technical Program Manager - Semiconductor & Memory Test Solutions
Milpitas, CA · On-site
$107K - $178K/yr
Drive cross-functional alignment across Design, DFT, Validation, Test Engineering, Product ... Strong understanding of semiconductor test methodologies, silicon validation, and manufacturing ...
Technical Program Manager - Semiconductor & Memory Test Solutions
Milpitas, CA · On-site
$107K - $178K/yr
Drive cross-functional alignment across Design, DFT, Validation, Test Engineering, Product ... Strong understanding of semiconductor test methodologies, silicon validation, and manufacturing ...
Drive cross-functional alignment across Design, DFT, Validation, Test Engineering, Product ... Strong understanding of semiconductor test methodologies, silicon validation, and manufacturing ...
Drive cross-functional alignment across Design, DFT, Validation, Test Engineering, Product ... Strong understanding of semiconductor test methodologies, silicon validation, and manufacturing ...
Staff/Principal ATE Test Engineer
$160K - $200K/yr
This role is focused primarily on semiconductor test engineering, spanning DFT collaboration, characterization support, wafer probe, final test, hardware development, production ramp, and ...
Staff/Principal ATE Test Engineer
$160K - $200K/yr
This role is focused primarily on semiconductor test engineering, spanning DFT collaboration, characterization support, wafer probe, final test, hardware development, production ramp, and ...
Drive cross-functional alignment across Design, DFT, Validation, Test Engineering, Product ... Strong understanding of semiconductor test methodologies, silicon validation, and manufacturing ...
Quick apply
Drive cross-functional alignment across Design, DFT, Validation, Test Engineering, Product ... Strong understanding of semiconductor test methodologies, silicon validation, and manufacturing ...
Vice President, CMOS Test Engineering & Test Operations
Santa Clara, CA · On-site
$211K - $272K/yr
About Marvell Marvell's semiconductor solutions are the essential building blocks of the data ... What You Can Expect Test Engineering Strategy & Execution * Own and drive the enterprise test ...
Vice President, CMOS Test Engineering & Test Operations
Santa Clara, CA · On-site
$211K - $272K/yr
About Marvell Marvell's semiconductor solutions are the essential building blocks of the data ... What You Can Expect Test Engineering Strategy & Execution * Own and drive the enterprise test ...
B achelor's degree or above in Electrical Engineering * 5+ years of recent experience in semiconductor test development, and/or some experience in silicon verification or emulation * Have 5 years of ...
B achelor's degree or above in Electrical Engineering * 5+ years of recent experience in semiconductor test development, and/or some experience in silicon verification or emulation * Have 5 years of ...
Senior Test Engineer
Austin, TX · On-site
B achelor's degree or above in Electrical Engineering * 5+ years of recent experience in semiconductor test development, and/or some experience in silicon verification or emulation * Have 5 years of ...
Senior Test Engineer
Austin, TX · On-site
B achelor's degree or above in Electrical Engineering * 5+ years of recent experience in semiconductor test development, and/or some experience in silicon verification or emulation * Have 5 years of ...
ATE Test Engineer
San Jose, CA · On-site
Collaborate with design, product engineering, and quality teams to optimize test strategies and ... Required Skills * 5+ years of semiconductor ATE experience. * Strong hands-on experience with ...
New
ATE Test Engineer
San Jose, CA · On-site
Collaborate with design, product engineering, and quality teams to optimize test strategies and ... Required Skills * 5+ years of semiconductor ATE experience. * Strong hands-on experience with ...
New
PhD in Electrical Engineering or closely related field with 9 years of experience * Direct ... semiconductor test software and hardware development experience * Prior test lead or test architect ...
PhD in Electrical Engineering or closely related field with 9 years of experience * Direct ... semiconductor test software and hardware development experience * Prior test lead or test architect ...
PhD in Electrical Engineering or closely related field with 9 years of experience * Direct ... semiconductor test software and hardware development experience * Prior test lead or test architect ...
PhD in Electrical Engineering or closely related field with 9 years of experience * Direct ... semiconductor test software and hardware development experience * Prior test lead or test architect ...
Required Qualifications: * 20+ years in semiconductor test/product engineering, postsilicon/postfab services, OSAT/foundry services, or related engineering services leadership. * Deep knowledge of ...
Required Qualifications: * 20+ years in semiconductor test/product engineering, postsilicon/postfab services, OSAT/foundry services, or related engineering services leadership. * Deep knowledge of ...
Semiconductor Test Technician
Santa Rosa, CA · On-site
$100/hr
Semiconductor Test Technician Pay Rate Range: $28.00/hr. Benefits include health, dental, and ... You will be part of a small, high-performing team and will work closely with engineering and ...
Quick apply
Semiconductor Test Technician
Santa Rosa, CA · On-site
$100/hr
Semiconductor Test Technician Pay Rate Range: $28.00/hr. Benefits include health, dental, and ... You will be part of a small, high-performing team and will work closely with engineering and ...
Director, ATE Test Engineering
Santa Clara, CA · On-site
$279K - $419K/yr
Ampere is a semiconductor design company for a new era, leading the future of computing with an ... Ampere is seeking a hands-on, high-impact leader to build and scale our ATE Test Engineering ...
Director, ATE Test Engineering
Santa Clara, CA · On-site
$279K - $419K/yr
Ampere is a semiconductor design company for a new era, leading the future of computing with an ... Ampere is seeking a hands-on, high-impact leader to build and scale our ATE Test Engineering ...
Director, ATE Test Engineering
Portland, OR · On-site
$279K - $419K/yr
Ampere is a semiconductor design company for a new era, leading the future of computing with an ... Ampere is seeking a hands-on, high-impact leader to build and scale our ATE Test Engineering ...
Director, ATE Test Engineering
Portland, OR · On-site
$279K - $419K/yr
Ampere is a semiconductor design company for a new era, leading the future of computing with an ... Ampere is seeking a hands-on, high-impact leader to build and scale our ATE Test Engineering ...
Overnight Semiconductor Test Engineering information
See salary details
$10.34 - $14.90
2% of jobs
$14.90 - $19.47
6% of jobs
$19.47 - $24.04
11% of jobs
$26.89 is the 25th percentile. Wages below this are outliers.
$24.04 - $28.61
8% of jobs
$28.61 - $33.17
7% of jobs
$33.17 - $37.74
5% of jobs
The median wage is $39.45 / hr.
$37.74 - $42.31
25% of jobs
$45.47 is the 75th percentile. Wages above this are outliers.
$42.31 - $46.88
14% of jobs
$46.88 - $51.44
7% of jobs
$51.44 - $56.01
6% of jobs
$56.01 - $60.58
7% of jobs
$10
$38
$60
How much do overnight semiconductor test engineering jobs pay per hour?
What is the difference between Overnight Semiconductor Test Engineering vs Day Shift Semiconductor Test Engineering?
| Aspect | Overnight Semiconductor Test Engineering | Day Shift Semiconductor Test Engineering |
|---|---|---|
| Work Hours | Typically overnight shifts, e.g., 10 PM - 6 AM | Standard daytime hours, e.g., 8 AM - 4 PM |
| Work Environment | Same manufacturing facilities, different shift schedules | Same facilities, different shift schedules |
| Credentials | Similar certifications, e.g., EE degree, test engineering experience | Similar credentials, same industry standards |
| Industry Usage | Common in 24/7 semiconductor manufacturing plants | Standard in semiconductor fabs operating during daytime |
Overnight Semiconductor Test Engineering and Day Shift Semiconductor Test Engineering share similar roles, responsibilities, and credentials. The primary difference lies in shift timing, with overnight engineers working during night hours to support continuous manufacturing operations. Both positions require comparable skills and are vital for maintaining production efficiency in semiconductor facilities.
Full-time
Re-posted 18 days ago
Nvidia rating
9.3
Based on 5 frontline employees who took The Breakroom Quiz
15th of 209 rated software companies
Job description
We are seeking a Staff/Principal Solutions Architect to define and lead the technical strategy for semiconductor test. This covers wafer and package test operations from start to finish. This senior individual contributor role is central to our manufacturing and product engineering teams. You will lead the architectural vision for device testing from wafer probe to final package test. Your directive includes modernising test infrastructure, improving yield, and embedding data-driven intelligence throughout the test lifecycle. You will partner closely with development, process, product engineering, and manufacturing teams across sites to ensure our test strategy scales with increasingly complex device portfolios.
What You'll be doing:
Define the comprehensive test development strategy across wafer-level (probe/ATE) and package/final/qual test for new and existing product families.
Lead architectural trade-off decisions on test coverage, test time, cost of test, and quality escapes across the full test flow.
Establish architectural guidelines for the test program, Test Methods/Class structure, modularity, and reuse across ATE platforms (Advantest, Teradyne, etc.).
Serve as the senior liaison between build and test engineering for DFT architecture decisions - scan, BIST, JTAG, boundary scan, and embedded compression.
Influence SoC and IP build reviews to ensure testability, observability, and debug-ability
Drive adoption of AI/ML techniques for yield learning, outlier detection, predictive binning, and test time optimization.
Define and maintain test roadmaps aligned to device technology roadmaps and manufacturing scale targets.
Mentor senior and principal test engineers; cultivate technical standards and guidelines across the test organisation.
Engage with ATE vendors, test IP providers, and industry consortia (SEMI, JEDEC, IEEE) on emerging standards and technology directions.
What we need to see:
15+ years of hands-on semiconductor test engineering experience within a fab, IDM, or OSAT environment.
Extensive knowledge in at least three of the following areas: ATE platform architecture, test program development, DFT methodology, yield analysis, or test data/ML analytics.
Skilled in leading ATE platforms such as Advantest V93000, Teradyne UltraFLEX/ETS, or similar systems.
Strong background in DFT architectures - scan compression, MBIST, LBIST, JTAG, and related methodologies.
Experience with mixed-signal, RF, or high-speed I/O test is highly valued.
Proficiency in test-related scripting and automation (Python, Perl, C++, or platform-native languages).
Proven ability to lead multi-site technical initiatives involving multi-functional teams and influence without direct authority.
MSEE, MSCE, MSCS, or related field (or equivalent experience).
Ways to stand out from the crowd
Experience applying ML/AI to yield analysis, PAT/GDBN outlier screening, or adaptive test.
Knowledge of test data formats (STDF, ATDF) and analytics tools (JMP, Spotfire, or custom).
Exposure to advanced packaging test challenges (2.5D/3D, chiplets, KGD).
Prior engagement with SEMI standards committees or ATE vendor co-development programs.
Ph.D or equivalent experience in related field
With competitive salaries and a generous benefits package, NVIDIA is widely considered to be one of the technology world's most desirable employers. We have some of the most thoughtful and dedicated people in the world working for us. Due to unprecedented growth, our best-in-class engineering teams are rapidly growing. If you're a creative and autonomous engineer with a real passion for technology, we want to hear from you.
Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. The base salary range is 216,000 USD - 345,000 USD.You will also be eligible for equity and benefits.
This posting is for an existing vacancy.
NVIDIA uses AI tools in its recruiting processes.
NVIDIA is committed to fostering an inclusive work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law.About Nvidia
Sourced by ZipRecruiter
NVIDIA has been transforming computer graphics, PC gaming, and accelerated computing for more than 25 years. It's a unique legacy of innovation that's fueled by great technology--and amazing people. Today, we're tapping into the unlimited potential of AI to define the next era of computing. An era in which our GPU acts as the brains of computers, robots, and self-driving cars that can understand the world. Doing what's never been done before takes vision, innovation, and the world's best talent.
Industry
Computer and electronic product manufacturing
Company size
10,000+ Employees
Headquarters location
Santa Clara, CA, US
Year founded
1993