... accelerators (GPU, NPU, FPGA, or custom ASIC) or parallel architectures Preferred : • Experience with machine learning compiler stacks (e.g., ONNX, MLIR, TVM, XLA, IREE, PyTorch), with ...
... accelerators (GPU, NPU, FPGA, or custom ASIC) or parallel architectures Preferred : • Experience with machine learning compiler stacks (e.g., ONNX, MLIR, TVM, XLA, IREE, PyTorch), with ...
... accelerators (GPU, NPU, FPGA, or custom ASIC) or parallel architectures Preferred : • Experience with machine learning compiler stacks (e.g., ONNX, MLIR, TVM, XLA, IREE, PyTorch), with ...
... accelerators (GPU, NPU, FPGA, or custom ASIC) or parallel architectures Preferred : • Experience with machine learning compiler stacks (e.g., ONNX, MLIR, TVM, XLA, IREE, PyTorch), with ...
... accelerators (GPU, NPU, FPGA, or custom ASIC) or parallel architectures Preferred : • Experience with machine learning compiler stacks (e.g., ONNX, MLIR, TVM, XLA, IREE, PyTorch), with ...
... accelerators (GPU, NPU, FPGA, or custom ASIC) or parallel architectures Preferred : • Experience with machine learning compiler stacks (e.g., ONNX, MLIR, TVM, XLA, IREE, PyTorch), with ...
... accelerators (GPU, NPU, FPGA, or custom ASIC) or parallel architectures Preferred : • Experience with machine learning compiler stacks (e.g., ONNX, MLIR, TVM, XLA, IREE, PyTorch), with ...
... accelerators (GPU, NPU, FPGA, or custom ASIC) or parallel architectures Preferred : • Experience with machine learning compiler stacks (e.g., ONNX, MLIR, TVM, XLA, IREE, PyTorch), with ...
Exposure to specialized accelerators (GPU, NPU, FPGA, or custom ASIC) or parallel architectures The following would be nice to have, but is not required * Experience with machine learning compiler ...
Quick apply
Exposure to specialized accelerators (GPU, NPU, FPGA, or custom ASIC) or parallel architectures The following would be nice to have, but is not required * Experience with machine learning compiler ...
Exposure to specialized accelerators (GPU, NPU, FPGA, or custom ASIC) or parallel architectures The following would be nice to have, but is not required * Experience with machine learning compiler ...
Exposure to specialized accelerators (GPU, NPU, FPGA, or custom ASIC) or parallel architectures The following would be nice to have, but is not required * Experience with machine learning compiler ...
Exposure to specialized accelerators (GPU, NPU, FPGA, or custom ASIC) or parallel architectures The following would be nice to have, but is not required * Experience with machine learning compiler ...
Exposure to specialized accelerators (GPU, NPU, FPGA, or custom ASIC) or parallel architectures The following would be nice to have, but is not required * Experience with machine learning compiler ...
Exposure to specialized accelerators (GPU, NPU, FPGA, or custom ASIC) or parallel architectures The following would be nice to have, but is not required * Experience with machine learning compiler ...
Quick apply
Exposure to specialized accelerators (GPU, NPU, FPGA, or custom ASIC) or parallel architectures The following would be nice to have, but is not required * Experience with machine learning compiler ...
Exposure to specialized accelerators (GPU, NPU, FPGA, or custom ASIC) or parallel architectures The following would be nice to have, but is not required * Experience with machine learning compiler ...
Exposure to specialized accelerators (GPU, NPU, FPGA, or custom ASIC) or parallel architectures The following would be nice to have, but is not required * Experience with machine learning compiler ...
Exposure to specialized accelerators (GPU, NPU, FPGA, or custom ASIC) or parallel architectures The following would be nice to have, but is not required * Experience with machine learning compiler ...
Exposure to specialized accelerators (GPU, NPU, FPGA, or custom ASIC) or parallel architectures The following would be nice to have, but is not required * Experience with machine learning compiler ...
Accelerator Compiler and Tool Chain Lead
Santa Clara, CA · On-site
$200K - $500K/yr
This role will lead the path fromcustomer AI models to optimized executable artifacts for our NPU, including graphimport, operator lowering, compiler IR, graph transformations, quantization ...
Accelerator Compiler and Tool Chain Lead
Santa Clara, CA · On-site
$200K - $500K/yr
This role will lead the path fromcustomer AI models to optimized executable artifacts for our NPU, including graphimport, operator lowering, compiler IR, graph transformations, quantization ...
Accelerator Compiler and Tool Chain Lead
Santa Clara, CA · On-site
$200K - $300K/yr
This role will lead the path from customer AI models to optimized executable artifacts for our NPU, including graph import, operator lowering, compiler IR, graph transformations, quantization ...
Accelerator Compiler and Tool Chain Lead
Santa Clara, CA · On-site
$200K - $300K/yr
This role will lead the path from customer AI models to optimized executable artifacts for our NPU, including graph import, operator lowering, compiler IR, graph transformations, quantization ...
Accelerator Compiler and Tool Chain Lead
Santa Clara, CA · On-site
$200K - $500K/yr
This role will lead the path from customer AI models to optimized executable artifacts for our NPU, including graph import, operator lowering, compiler IR, graph transformations, quantization ...
Accelerator Compiler and Tool Chain Lead
Santa Clara, CA · On-site
$200K - $500K/yr
This role will lead the path from customer AI models to optimized executable artifacts for our NPU, including graph import, operator lowering, compiler IR, graph transformations, quantization ...
$250/hr
AI runtimes and execution engines with emphasis on graphs spanning multiple NPU. * Compiler technologies and graph optimization * ML frameworks and ecosystem enablement * Platform SDKs, APIs, tools ...
$250/hr
AI runtimes and execution engines with emphasis on graphs spanning multiple NPU. * Compiler technologies and graph optimization * ML frameworks and ecosystem enablement * Platform SDKs, APIs, tools ...
Sr. Director, Engineering San Diego, California, United States of America Software Engineering
San Diego, CA · On-site
$250/hr
AI runtimes and execution engines with emphasis on graphs spanning multiple NPU. * Compiler technologies and graph optimization * ML frameworks and ecosystem enablement * Platform SDKs, APIs, tools ...
Sr. Director, Engineering San Diego, California, United States of America Software Engineering
San Diego, CA · On-site
$250/hr
AI runtimes and execution engines with emphasis on graphs spanning multiple NPU. * Compiler technologies and graph optimization * ML frameworks and ecosystem enablement * Platform SDKs, APIs, tools ...
Define and evolve the NPU core microarchitecture, including compute datapaths, instruction flow ... Rivian's compiler flow translates neural network model descriptions into raw instruction streams ...
Define and evolve the NPU core microarchitecture, including compute datapaths, instruction flow ... Rivian's compiler flow translates neural network model descriptions into raw instruction streams ...
... and NPU - ensuring models compile correctly, execute efficiently, and scale across a growing ... What You'll Do Compiler Pipeline & Infrastructure * Design, develop, and maintain the end-to-end ...
... and NPU - ensuring models compile correctly, execute efficiently, and scale across a growing ... What You'll Do Compiler Pipeline & Infrastructure * Design, develop, and maintain the end-to-end ...
Define and evolve the NPU core microarchitecture, including compute datapaths, instruction flow ... Rivian's compiler flow translates neural network model descriptions into raw instruction streams ...
Define and evolve the NPU core microarchitecture, including compute datapaths, instruction flow ... Rivian's compiler flow translates neural network model descriptions into raw instruction streams ...
Staff Machine Learning Engineer - AI/ML Compiler
Santa Clara, CA · On-site
$160K - $240K/yr
Join the Qualcomm AI Hub Compiler team and own the infrastructure that powers these model ... and NPU -- ensuring models compile correctly, execute efficiently, and scale across a growing ...
Staff Machine Learning Engineer - AI/ML Compiler
Santa Clara, CA · On-site
$160K - $240K/yr
Join the Qualcomm AI Hub Compiler team and own the infrastructure that powers these model ... and NPU -- ensuring models compile correctly, execute efficiently, and scale across a growing ...
Principal Software Engineer- Compute Graph Compiler (CGC) Team
Redmond, WA · On-site
$151K - $202K/yr
Overview The Compute Graph Compiler (CGC) team within DirectX is building core compiler and ... Drive NPU enablement strategy and advanced optimization techniques for next-generation AI ...
Principal Software Engineer- Compute Graph Compiler (CGC) Team
Redmond, WA · On-site
$151K - $202K/yr
Overview The Compute Graph Compiler (CGC) team within DirectX is building core compiler and ... Drive NPU enablement strategy and advanced optimization techniques for next-generation AI ...
Npu Compiler information
What is an NPU compiler?
An NPU Compiler is specialized software that translates high-level machine learning models or code into instructions optimized for Neural Processing Units (NPUs). NPUs are hardware accelerators designed to efficiently execute deep learning and AI workloads. The compiler bridges the gap between standard AI frameworks and the unique architecture of NPUs, optimizing computations for speed and power efficiency. It ensures that neural network operations are executed correctly and efficiently, often handling tasks like operator fusion, quantization, and hardware-specific optimization.
What are the key skills and qualifications needed to thrive as an NPU compiler engineer?
To thrive as an NPU Compiler Engineer, you need a strong background in computer science, compiler theory, and experience with neural network architectures, often supported by a degree in computer engineering or a related field. Familiarity with programming languages like C++, Python, and frameworks such as TensorFlow or PyTorch, as well as experience with hardware description languages and specialized compilers, is typically required. Excellent problem-solving skills, attention to detail, and effective collaboration are vital soft skills in this role. These competencies are crucial for optimizing neural network models to run efficiently on specialized hardware, ensuring high-performance and reliable AI solutions.
What are some common challenges faced by NPU compiler engineers, and how can they be addressed?
NPU Compiler engineers often encounter challenges related to optimizing code for specialized hardware, such as balancing performance with power consumption and ensuring compatibility across different neural processing unit architectures. Debugging and profiling code can also be complex due to the parallel nature of NPUs and limited visibility into hardware operations. To address these challenges, engineers frequently collaborate with hardware teams, utilize advanced profiling tools, and stay updated on the latest compiler optimization techniques. Building a strong foundation in both software and hardware principles is essential for success in this role.
What is the difference between Npu Compiler vs Hardware Engineer?
| Aspect | Npu Compiler | Hardware Engineer |
|---|---|---|
| Required Credentials | Bachelor's or higher in Computer Science, Electrical Engineering, or related fields; knowledge of hardware description languages | Bachelor's or higher in Electrical Engineering, Computer Engineering, or related fields; certifications like CCNA or Cisco certifications are common |
| Work Environment | Software development teams, AI and hardware integration labs, R&D departments | Design labs, manufacturing facilities, R&D departments |
| Industry Usage | AI hardware, embedded systems, chip design companies | Semiconductor companies, consumer electronics, hardware manufacturing |
The Npu Compiler focuses on developing software tools that optimize and translate neural network models for AI hardware, while Hardware Engineers design and develop physical hardware components. Both roles often collaborate but serve different parts of the hardware-software ecosystem in AI and electronics industries.
What are popular job titles related to Npu Compiler jobs?
For Npu Compiler jobs, the most frequently searched job titles are:
Compiler Engineer - Machine Learning Compiler
Remote
Mythic
Full-time
Re-posted 7 days ago
Job description
Job Summary:
Mythic is building the future of AI computing with breakthrough analog technology. The role involves developing the compiler for their novel AI accelerator, collaborating with hardware engineers and ML researchers to optimize deep learning workloads on cutting-edge dataflow hardware.
Responsibilities:
• Contribute across the full compiler stack, including operator lowering, graph/IR transformations, optimization passes, and backend code generation
• Optimize for dataflow architectures, developing pipelined schedules, memory orchestration, and resource-constrained execution strategies
• Collaborate with hardware architects to influence architectural features, ensuring the compiler and hardware evolve together
• Develop compilation strategies that unify our analog compute with digital subsystems
• Build and maintain a compiler that produces high-performance binaries with strong debugging support, clear error messages, and predictable performance models
Qualifications:
Required:
• 3+ years of experience building compilers or high-performance systems software, especially those involving complex resource management or optimization.
• Expert in modern C++ (C++14/17/20) and strong Python.
• Experience with compiler IRs (SSA-based or graph-based), transformations, and code generation
• Exposure to specialized accelerators (GPU, NPU, FPGA, or custom ASIC) or parallel architectures
Preferred:
• Experience with machine learning compiler stacks (e.g., ONNX, MLIR, TVM, XLA, IREE, PyTorch), with contributions to MLIR or LLVM projects a plus
• Experience with optimization methods (LP/MIP, CP, SAT/SMT) using solvers like Gurobi or OR-Tools for scheduling and resource allocation
• Experience compiling for specialized accelerators (GPU, NPU, FPGA, or custom ASIC) on DNN workloads; GPU/DSP experience is valuable if combined with compiler backend work beyond kernel tuning
• Familiarity with heterogeneous compilation, especially mixing custom accelerators with CPUs/GPUs/NPUs, and exposure to analog or in-memory compute is a plus
• Experience collaborating in compiler–hardware co-design (architecture + ISA) for better compiler usability and hardware efficiency
Company:
Mythic develops analog matrix processors and key cards based on analog compute-in-memory. Founded in 2012, the company is headquartered in Austin, USA, with a team of 51-200 employees. The company is currently Early Stage.
Mythic is building the future of AI computing with breakthrough analog technology. The role involves developing the compiler for their novel AI accelerator, collaborating with hardware engineers and ML researchers to optimize deep learning workloads on cutting-edge dataflow hardware.
Responsibilities:
• Contribute across the full compiler stack, including operator lowering, graph/IR transformations, optimization passes, and backend code generation
• Optimize for dataflow architectures, developing pipelined schedules, memory orchestration, and resource-constrained execution strategies
• Collaborate with hardware architects to influence architectural features, ensuring the compiler and hardware evolve together
• Develop compilation strategies that unify our analog compute with digital subsystems
• Build and maintain a compiler that produces high-performance binaries with strong debugging support, clear error messages, and predictable performance models
Qualifications:
Required:
• 3+ years of experience building compilers or high-performance systems software, especially those involving complex resource management or optimization.
• Expert in modern C++ (C++14/17/20) and strong Python.
• Experience with compiler IRs (SSA-based or graph-based), transformations, and code generation
• Exposure to specialized accelerators (GPU, NPU, FPGA, or custom ASIC) or parallel architectures
Preferred:
• Experience with machine learning compiler stacks (e.g., ONNX, MLIR, TVM, XLA, IREE, PyTorch), with contributions to MLIR or LLVM projects a plus
• Experience with optimization methods (LP/MIP, CP, SAT/SMT) using solvers like Gurobi or OR-Tools for scheduling and resource allocation
• Experience compiling for specialized accelerators (GPU, NPU, FPGA, or custom ASIC) on DNN workloads; GPU/DSP experience is valuable if combined with compiler backend work beyond kernel tuning
• Familiarity with heterogeneous compilation, especially mixing custom accelerators with CPUs/GPUs/NPUs, and exposure to analog or in-memory compute is a plus
• Experience collaborating in compiler–hardware co-design (architecture + ISA) for better compiler usability and hardware efficiency
Company:
Mythic develops analog matrix processors and key cards based on analog compute-in-memory. Founded in 2012, the company is headquartered in Austin, USA, with a team of 51-200 employees. The company is currently Early Stage.