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Npu Compiler Jobs (NOW HIRING)

... NPU, DSP, GPU, or VLIW compiler development Custom MLIR dialects and hardware-specific IRs Static scheduling and software-managed memory DMA engines and multi-level memory hierarchies Quantization ...

... NPU, DSP, GPU, or VLIW compiler development • Custom MLIR dialects and hardware-specific IRs • Static scheduling and software-managed memory • DMA engines and multi-level memory hierarchies • ...

Software Development Manager - Compiler

Cupertino, CA · On-site

$152K - $201K/yr

As a Manager III you be leading a team of experienced compiler engineers developing compiler ... NPU, GPU and novel forms of compute. Explore the Product: In order to be considered for this role ...

Software Development Manager - Compiler

Cupertino, CA · On-site

$152K - $201K/yr

As a Manager III you be leading a team of experienced compiler engineers developing compiler ... NPU, GPU and novel forms of compute. Explore the Product: In order to be considered for this role ...

Software Development Manager - Compiler

Cupertino, CA · On-site

$152K - $201K/yr

As a Manager III you be leading a team of experienced compiler engineers developing compiler ... NPU, GPU and novel forms of compute. Explore the Product: In order to be considered for this role ...

You may have shipped models across multiple NPU or edge silicon targets and felt the per-vendor toolchain and optimization tax firsthand. * You may have built inference deployment, compiler, or mixed ...

Experience designing custom ISAs or novel accelerator architectures (TPU, NPU, or similar) * Familiarity with what makes an ISA compiler-friendly, with awareness of the downstream software ...

Senior Silicon Emulation Engineer

Austin, TX · On-site

$103K - $142K/yr

Experience with NPU, DSP, or GPU-class accelerators * Experience running or debugging ML inference workloads on pre-silicon platforms * Knowledge of AI software stacks (runtime, compiler, graph ...

Forward Deployed Engineer

Burlingame, CA · On-site

$175K - $225K/yr

Build deep fluency across the Chimera stack - quantization, custom kernels, and compiler tooling ... Background at NPU/edge-AI IP and silicon companies (e.g., Qualcomm SNPE/QNN, NVIDIA TensorRT/Jetson ...

Experience with NPU, DSP, or GPU-class accelerators * Experience running or debugging ML inference workloads on pre-silicon platforms * Knowledge of AI software stacks (runtime, compiler, graph ...

Experience with NPU, DSP, or GPU-class accelerators * Experience running or debugging ML inference workloads on pre-silicon platforms * Knowledge of AI software stacks (runtime, compiler, graph ...

Forward Deployed Engineer

Burlingame, CA · On-site

$175K - $225K/yr

Build deep fluency across the Chimera stack -- quantization, custom kernels, and compiler tooling ... Background at NPU/edge-AI IP and silicon companies (e.g., Qualcomm SNPE/QNN, NVIDIA TensorRT/Jetson ...

Showing results 21-40

Npu Compiler information

What is an NPU compiler?

An NPU Compiler is specialized software that translates high-level machine learning models or code into instructions optimized for Neural Processing Units (NPUs). NPUs are hardware accelerators designed to efficiently execute deep learning and AI workloads. The compiler bridges the gap between standard AI frameworks and the unique architecture of NPUs, optimizing computations for speed and power efficiency. It ensures that neural network operations are executed correctly and efficiently, often handling tasks like operator fusion, quantization, and hardware-specific optimization.

What are the key skills and qualifications needed to thrive as an NPU compiler engineer?

To thrive as an NPU Compiler Engineer, you need a strong background in computer science, compiler theory, and experience with neural network architectures, often supported by a degree in computer engineering or a related field. Familiarity with programming languages like C++, Python, and frameworks such as TensorFlow or PyTorch, as well as experience with hardware description languages and specialized compilers, is typically required. Excellent problem-solving skills, attention to detail, and effective collaboration are vital soft skills in this role. These competencies are crucial for optimizing neural network models to run efficiently on specialized hardware, ensuring high-performance and reliable AI solutions.

What are some common challenges faced by NPU compiler engineers, and how can they be addressed?

NPU Compiler engineers often encounter challenges related to optimizing code for specialized hardware, such as balancing performance with power consumption and ensuring compatibility across different neural processing unit architectures. Debugging and profiling code can also be complex due to the parallel nature of NPUs and limited visibility into hardware operations. To address these challenges, engineers frequently collaborate with hardware teams, utilize advanced profiling tools, and stay updated on the latest compiler optimization techniques. Building a strong foundation in both software and hardware principles is essential for success in this role.

What is the difference between Npu Compiler vs Hardware Engineer?

AspectNpu CompilerHardware Engineer
Required CredentialsBachelor's or higher in Computer Science, Electrical Engineering, or related fields; knowledge of hardware description languagesBachelor's or higher in Electrical Engineering, Computer Engineering, or related fields; certifications like CCNA or Cisco certifications are common
Work EnvironmentSoftware development teams, AI and hardware integration labs, R&D departmentsDesign labs, manufacturing facilities, R&D departments
Industry UsageAI hardware, embedded systems, chip design companiesSemiconductor companies, consumer electronics, hardware manufacturing

The Npu Compiler focuses on developing software tools that optimize and translate neural network models for AI hardware, while Hardware Engineers design and develop physical hardware components. Both roles often collaborate but serve different parts of the hardware-software ecosystem in AI and electronics industries.

What are popular job titles related to Npu Compiler jobs?

For Npu Compiler jobs, the most frequently searched job titles are:

Infographic showing various Npu Compiler job openings in the United States as of September 2026, with employment types broken down into 1% Internship, 95% Full Time, 1% Part Time, 1% Temporary, and 2% Contract. Highlights an 86% Physical, 4% Hybrid, and 10% Remote job distribution.

Staff Compiler Design Engineer

Austin, TX • On-site

Ericsson
IT Services • 10K+ employees

Full-time

Medical, Dental, Life, Retirement, PTO

Re-posted 10 days ago


Ericsson rating

9.2

Company rating: 9.2 out of 10

Based on 17 frontline employees who took The Breakroom Quiz

2nd of 101 rated telecommunications companies


Job description

Grow with us Staff Compiler Engineer, Principal level Austin, Texas This is not a remote work opportunity. The Mission We are building an MLIR-based compiler and inference stack for custom AI silicon used in telecommunications baseband processing. The compiler takes ML models from StableHLO through orchestration, tiling, memory planning, and code generation onto a multi-core processor architecture with custom accelerators.

We already have a working proof point. Real workloads are running on custom silicon at competitive perf-per-watt, and we are building the general-purpose compiler stack around it. This is a small team building something real, not a research project.

We are hiring a Principal Compiler Engineer to lead the technical direction of the compiler stack while remaining hands-on in the code. You will make the hard architectural calls, own the pieces of the compiler that determine whether it succeeds, and mentor a growing team of senior compiler engineers. We believe the best architecture comes from the people implementing the system, not from a separate role.

This is a hands-on technical leadership role. You will architect, code, review, debug, and profile. If you are looking for a role where you design without shipping, this is not it.

You will work directly with hardware architects, runtime developers, and AI researchers, and you will shape both the compiler and how the team builds it. What you will do Own the technical direction of the compiler stack across model import, lowering, scheduling, memory planning, and code generation Design and implement the hardest compiler subsystems, the ones that determine whether the compiler achieves its performance and correctness goals Define MLIR dialect hierarchy, lowering strategy, and pass pipelines in collaboration with the team Lead hardware-software co-design discussions, partnering with hardware architects to influence instruction set, memory hierarchy, and synchronization mechanisms Set the technical standards for correctness, determinism, testing, and performance Mentor Staff and Senior compiler engineers, and shape the technical growth of the team Represent the compiler team in cross-org technical discussions and roadmap planning Long Description The role requires both breadth, reasoning across the full compiler stack, and depth, going deep on whatever subsystem needs it most at a given moment. We expect this person to move fluidly between architecture, implementation, debugging, and performance analysis.

Core qualifications Deep experience designing and building production compilers, including significant hands-on ownership of major subsystems Strong C++ and compiler infrastructure expertise Hands-on experience with MLIR, LLVM, or another production compiler framework at scale Track record of shipping compiler work that others build on Strong understanding of computer architecture and how compilers exploit hardware capabilities Ability to lead complex technical programs across compiler and hardware teams Experience mentoring senior engineers and shaping team-level technical decisions Additional Preferred Experience AI accelerator, NPU, DSP, GPU, or VLIW compiler development Custom MLIR dialects and hardware-specific IRs Static scheduling and software-managed memory DMA engines and multi-level memory hierarchies Quantization, fixed-point, mixed precision, or complex arithmetic Bare-metal or embedded inference environments Runtime, firmware, or device-driver integration Hardware-software co-design for new silicon StableHLO, XLA, JAX, PyTorch, TensorFlow, or ONNX The ideal candidate has deep compiler expertise, can reason across the complete inference flow from framework-level model representation to execution on custom silicon, and wants to remain hands-on rather than move into pure architecture or management. What happens once you apply. Click Here to find all you need to know about what our typical hiring process looks like.

Ericsson uses a merit-based hiring approach that values people with different experiences, perspectives and skillsets. We truly believe this approach drives innovation, which is essential for our future growth. We encourage people from all backgrounds to apply and realize their full potential as part of our Ericsson team.

Ericsson is proud to be an Equal Opportunity employer, learn more. If you need assistance or to request an accommodation due to a disability, please contact Ericsson at hr.direct.americas@ericsson.com. DISCLAIMER: The above statements are intended to describe the general nature and level of work being performed by employees in this position

They are not an exhaustive list of all responsibilities, duties and skills required for this position, and you may be required to perform additional job tasks as assigned. Primary country and city: USA || Austin, Texas Job details: Developer Primary Recruiter: Jim Everett Compensation and Benefits at Ericsson At Ericsson, we know that our people are the key to our success. We offer a competitive package to help with your individual needs and goals.

Your Pay The salary range for this position is dependent on various factors including, but not limited to, location, and the candidate's Short-Term Variable Compensation Plan (select STV or SIP): Your pay also includes the opportunity for an annual bonus. Actual bonus payouts are based on performance of the business against the unit's objectives, individual performance, and the individual bonus target. Certain eligibility and pro-ration rules apply.

Your Health Ericsson offers excellent health benefits including the choice of three medical plan options and a dental plan option that allow an employee to select the level of coverage that suits their needs. Employees will receive company credits in an amount equal to the cost that Ericsson pays toward the cost of their medical and dental premiums for themselves and eligible covered dependents. Your Financial Security We invest in both your short and long-term financial wellbeing.

The Ericsson US 401(k) Plan offers an automatic 3% company contribution and Ericsson match $1 for every $1 you put into the 401(k) Plan on the first 3% of your eligible pay, plus 50 cents on every $1 on the next 2% of eligible pay. When you contribute at least 5% of eligible pay, you are receiving Ericsson's full matching contributions of 4%. Matching and company automatic contributions stop when your total eligible pay for the year reaches the IRS limits.

Employees will also receive company credits in an amount equal to the cost of basic life insurance and basic accidental death and dismemberment coverage, as well as short-term and long-term disability coverage. Employees also have the option to participate in Ericsson's Stock Purchase Plan. Your Time Your work-life balance is important to us.

New employees are provided a minimum of 15 days of accrued vacation, up to 3 personal days per year, 11 annual holidays, 8 hours of volunteer time, and 80 hours of sick time annually. Please note paid time off is pro-rated based on the employee's start date. Furthermore, Ericsson provides up to 16 weeks of paid maternity leave and 6 weeks of parental or adoption leave at 100% of pay.

Additional Benefits Ericsson offers many other company-paid benefits such as financial wellness programs, educational assistance, matching gifts, and recognition programs.


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