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New Grad Asic Design Verification Engineer Jobs in Bothell, WA

Capgemini Engineering

ASIC Verification Engineer

Seattle, WA · On-site

$76.20K - $187.74K/yr

ASIC verification Engineer The role is 100% remote role About the job you're considering We are ... Work closely with other teams to gather relevant information and share design insights to improve ...

Capgemini

ASIC Verification Engineer

Seattle, WA · On-site +1

$76.20K - $187.74K/yr

ASIC Verification Engineer At Capgemini Engineering, the world leader in engineering services, we ... Work closely with other teams to gather relevant information and share design insights to improve ...

United Airlines

ASIC Verification Engineer

Seattle, WA

$76.20K - $187.74K/yr

ASIC verification Engineer The role is 100% remote role About the job you're considering We are ... Work closely with other teams to gather relevant information and share design insights to improve ...

Capgemini Engineering

ASIC Verification Engineer

Seattle, WA · On-site +1

$76.20K - $187.74K/yr

... an ASIC Verification Engineer with hands-on experience working on ARM-related IPs such as CPU ... Work closely with other teams to gather relevant information and share design insights to improve ...

Apple

Design Verification Engineer

Seattle, WA

$139.50K - $258.10K/yr

At Apple, our new ideas have a way of becoming great products, services, and customer experiences ... Design Verification Engineers at Apple are responsible for verifying the functionality and ...

Nytec, Inc.

Design Verification Engineer - EE

Redmond, WA · On-site

$152.30K - $185.90K/yr

Our large enterprise client is looking for a strong Design Verification Engineer with Electrical ... Develop new and modify existing tests with creative ideas and simplification * Be concise and clear ...

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All JobsNew Grad Asic Design Verification Engineer JobsNew Grad Asic Design Verification Engineer Jobs in Bothell, WA

New Grad Asic Design Verification Engineer information

See Bothell, WA salary details

$117.9K

$166.7K

$186.7K

How much do new grad asic design verification engineer jobs pay per year?

As of May 29, 2026, the average yearly pay for new grad asic design verification engineer in Bothell, WA is $166,733.00, according to ZipRecruiter salary data. Most workers in this role earn between $152,000.00 and $185,600.00 per year, depending on experience, location, and employer.

What are the key skills and qualifications needed to thrive as a New Grad ASIC Design Verification Engineer, and why are they important?

To thrive as a New Grad ASIC Design Verification Engineer, you need a solid understanding of digital design principles, hardware description languages (such as Verilog or VHDL), and a relevant degree in electrical or computer engineering. Familiarity with industry-standard verification tools and environments like SystemVerilog, UVM, and simulation/debugging platforms is typically required. Strong analytical thinking, attention to detail, and effective teamwork skills help you excel in diagnosing issues and collaborating with design teams. These skills and qualities ensure robust verification processes that lead to functional, reliable ASIC products.

What are some common challenges new graduates face when starting as an ASIC Design Verification Engineer, and how can they overcome them?

New grad ASIC Design Verification Engineers often encounter challenges such as understanding complex verification environments, learning industry-standard tools and methodologies like UVM, and effectively debugging hardware designs. To overcome these, it's helpful to actively seek mentorship from experienced team members, participate in code reviews, and utilize available documentation and training resources. Collaborating closely with designers and verification leads, asking questions, and consistently practicing hands-on simulations can accelerate learning and build confidence in tackling verification tasks.

What does a New Grad ASIC Design Verification Engineer do?

A New Grad ASIC Design Verification Engineer is responsible for testing and validating the design of Application-Specific Integrated Circuits (ASICs) to ensure they meet functional and performance specifications. They typically create testbenches, develop verification plans, write test cases using hardware description languages like SystemVerilog, and debug issues found during simulations. This role is crucial for catching design flaws before manufacturing, working closely with design engineers and using both manual and automated verification methods. As a new graduate, you will learn industry-standard verification methodologies and tools while contributing to the success of the silicon development process.

What is the difference between New Grad Asic Design Verification Engineer vs New Grad Digital Design Engineer?

AspectNew Grad Asic Design Verification EngineerNew Grad Digital Design Engineer
Required SkillsHardware verification, simulation, scripting, HDL knowledgeDigital circuit design, HDL coding, logic design
Work EnvironmentVerification labs, simulation tools, hardware testingDesign teams, FPGA/ASIC development, coding
Industry UsagePrimarily in semiconductor and chip companiesBroadly in electronics, semiconductor, and tech firms

While both roles require HDL knowledge and work in semiconductor environments, the New Grad Asic Design Verification Engineer focuses on verifying and testing ASIC designs, whereas the New Grad Digital Design Engineer is involved in designing digital circuits. Both roles are essential in chip development but differ in their primary responsibilities and skill emphasis.

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New Grad Asic Design Verification Engineer jobs near you
Sr. ASIC Design Verification Engineer (Silicon Engineering)

Sr. ASIC Design Verification Engineer (Silicon Engineering)

SpaceX

Redmond, WA • On-site

$165K - $230K/yr

Other

Medical, Dental, Vision, Life, Retirement, PTO

Posted 8 days ago

SpaceX rating

8.7

Company rating: 8.7 out of 10

Based on 142 frontline employees who took The Breakroom Quiz

12th of 59 rated aerospace companies

Job description

SR. ASIC DESIGN VERIFICATION ENGINEER (SILICON ENGINEERING)

At SpaceX we're leveraging our experience in building rockets and spacecraft to deploy Starlink, the world's most advanced broadband internet system. Starlink is the world's largest satellite constellation and is providing fast, reliable internet to millions of users worldwide. We design, build, test, and operate all parts of the system - thousands of satellites, consumer receivers that allow users to connect within minutes of unboxing, and the software that brings it all together. We've only begun to scratch the surface of Starlink's potential global impact are looking for best-in-class engineers to help maximize Starlink's utility for communities and businesses around the globe. 

We are seeking a motivated, proactive, and intellectually curious engineer who will work alongside world-class cross-disciplinary teams (systems, firmware, architecture, design, validation, product engineering, ASIC implementation). In this role, you will be developing cutting-edge next-generation ASICs for deployment in space and ground infrastructures around the globe. These chips are enabling connectivity in places it has previously not been available, affordable or reliable. Your efforts will help deliver cutting-edge solutions that will expand the performance and capabilities of the Starlink network.   

RESPONSIBILITIES:

  • Responsible for digital ASIC verification at block and system level
  • Write and review test plans, develop test harnesses and test sequences
  • Responsible for test plan execution, running regressions, code and functional coverage closure
  • Contribute towards pre-silicon verification, chip bring-up and post-silicon validation
  • Be a hands-on self-starter who can execute the steps required to fully verify a complex digital designs

BASIC QUALIFICATIONS:

  • Bachelor's degree in electrical engineering or computer engineering
  • 5+ years of experience with design verification and test bench development

PREFERRED SKILLS AND EXPERIENCE:

  • Advanced degree in electrical engineering or computer engineering
  • Experience with verification methodologies such as UVM/OVM/VMM
  • Strong object-oriented programming knowledge
  • Strong problem-solving and coding skills
  • Experience in constrained random verification
  • Expertise in developing test plans, implementing coverage models, and analyzing results
  • Experience with scripting languages, e.g. Python for automation
  • RTL design, chip bring-up, and post-silicon validation experience
  • Ability to work in a dynamic environment with changing needs and requirements

ADDITIONAL REQUIREMENTS:

  • Ability to work extended hours and weekends as needed to meet critical milestones

COMPENSATION & BENEFITS:    

Pay range:    
Design Verification Engineer /Senior: $165,000.00 - $230,000.00/per year    
Your actual level and base salary will be determined on a case-by-case basis and may vary based on the following considerations: job-related knowledge and skills, education, and experience.

Base salary is just one part of your total rewards package at SpaceX. You may also be eligible for long-term incentives, in the form of company stock, stock options, or long-term cash awards, as well as potential discretionary bonuses and the ability to purchase additional stock at a discount through an Employee Stock Purchase Plan. You will also receive access to comprehensive medical, vision, and dental coverage, access to a 401(k) retirement plan, short & long-term disability insurance, life insurance, paid parental leave, and various other discounts and perks. You may also accrue 3 weeks of paid vacation & will be eligible for 10 or more paid holidays per year. Exempt employees are eligible for 5 days of sick leave per year.

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