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New Grad Asic Design Verification Engineer Jobs in Texas

Correct Designs

Design Verification Engineer

Austin, TX

$134K - $164K/yr

Austin, TX More about this job > Description Design Verification Engineer Looking for new ... Opportunities span from projects in AI and Machine Learning, processor fabric subsystems, SOC/ASIC ...

Correct Designs

Design Verification Engineer

Austin, TX

$134K - $164K/yr

Austin, TX More about this job > Description Design Verification Engineer Looking for new ... Opportunities span from projects in AI and Machine Learning, processor fabric subsystems, SOC/ASIC ...

Nvidia

Senior ASIC Verification Engineer

Austin, TX · Hybrid

NVIDIA is looking for a Senior ASIC Verification Engineer to help verify our global IP! This ... In this position, you will partner with the design and architecture teams to help make the right ...

Apple

Design Verification Engineer

Austin, TX · On-site

$134K - $164K/yr

Every new product we build, service we create, or Apple Store experience we deliver is the result ... We're looking for engineers with hands-on ASIC design verification experience using reusable ...

Apple

Design Verification Engineer

Austin, TX · On-site

$134K - $164K/yr

Every new product we build, service we create, or Apple Store experience we deliver is the result ... We're looking for engineers with hands-on ASIC design verification experience using reusable ...

Correct Designs

Design Verification Engineer

Austin, TX · On-site

$134K - $164K/yr

Design Verification Engineer Looking for new challenges? Would you like the variety of a contract ... Opportunities span from projects in AI and Machine Learning, processor fabric subsystems, SOC/ASIC ...

Correct Designs

Design Verification Engineer

Austin, TX · On-site

$134K - $164K/yr

Design Verification Engineer Looking for new challenges? Would you like the variety of a contract ... Opportunities span from projects in AI and Machine Learning, processor fabric subsystems, SOC/ASIC ...

Apple

Design Verification Engineer

Austin, TX

$122K - $214K/yr

Every new product we build, service we create, or Apple Store experience we deliver is the result ... We're looking for engineers with hands-on ASIC design verification experience using reusable ...

Apple

Design Verification Engineer

Austin, TX

$175K - $308K/yr

Every new product we build, service we create, or Apple Store experience we deliver is the result ... We're looking for engineers with hands-on ASIC design verification experience using reusable ...

Ericsson

ASIC Verification Engineer

Austin, TX · On-site

Design Verification Engineer - ASIC IP Company: Ericsson Silicon Location: Austin, Texas This is an ... You have a positive attitude, embrace new challenges, and recognize that change brings opportunity.

Apple

Design Verification Engineer

Austin, TX

$175K - $308K/yr

Every new product we build, service we create, or Apple Store experience we deliver is the result ... We're looking for engineers with hands-on ASIC design verification experience using reusable ...

Apple

Design Verification Engineer

Austin, TX

$122K - $214K/yr

Every new product we build, service we create, or Apple Store experience we deliver is the result ... We're looking for engineers with hands-on ASIC design verification experience using reusable ...

Etched

Design Verification Engineer - SoC

Austin, TX · On-site

$100 - $130/hr

Job Summary We are seeking a Design Verification Engineer to join our Systems/Performance ... Strong understanding of digital design, RTL, and ASIC design flows. * Hands-on experience with ...

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New Grad Asic Design Verification Engineer information

What does a new grad ASIC design verification engineer do?

A New Grad ASIC Design Verification Engineer is responsible for testing and validating the design of Application-Specific Integrated Circuits (ASICs) to ensure they meet functional and performance specifications. They typically create testbenches, develop verification plans, write test cases using hardware description languages like SystemVerilog, and debug issues found during simulations. This role is crucial for catching design flaws before manufacturing, working closely with design engineers and using both manual and automated verification methods. As a new graduate, you will learn industry-standard verification methodologies and tools while contributing to the success of the silicon development process.

What are the key skills and qualifications needed to thrive as a new grad ASIC design verification engineer?

To thrive as a New Grad ASIC Design Verification Engineer, you need a solid understanding of digital design principles, hardware description languages (such as Verilog or VHDL), and a relevant degree in electrical or computer engineering. Familiarity with industry-standard verification tools and environments like SystemVerilog, UVM, and simulation/debugging platforms is typically required. Strong analytical thinking, attention to detail, and effective teamwork skills help you excel in diagnosing issues and collaborating with design teams. These skills and qualities ensure robust verification processes that lead to functional, reliable ASIC products.

What is the difference between New Grad Asic Design Verification Engineer vs New Grad Digital Design Engineer?

AspectNew Grad Asic Design Verification EngineerNew Grad Digital Design Engineer
Required SkillsHardware verification, simulation, scripting, HDL knowledgeDigital circuit design, HDL coding, logic design
Work EnvironmentVerification labs, simulation tools, hardware testingDesign teams, FPGA/ASIC development, coding
Industry UsagePrimarily in semiconductor and chip companiesBroadly in electronics, semiconductor, and tech firms

While both roles require HDL knowledge and work in semiconductor environments, the New Grad Asic Design Verification Engineer focuses on verifying and testing ASIC designs, whereas the New Grad Digital Design Engineer is involved in designing digital circuits. Both roles are essential in chip development but differ in their primary responsibilities and skill emphasis.

What are some common challenges new graduates face when starting as an ASIC design verification engineer, and how can they overcome them?

New grad ASIC Design Verification Engineers often encounter challenges such as understanding complex verification environments, learning industry-standard tools and methodologies like UVM, and effectively debugging hardware designs. To overcome these, it's helpful to actively seek mentorship from experienced team members, participate in code reviews, and utilize available documentation and training resources. Collaborating closely with designers and verification leads, asking questions, and consistently practicing hands-on simulations can accelerate learning and build confidence in tackling verification tasks.
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New Grad Asic Design Verification Engineer jobs near you

ASIC Engineer, Power Management Design Verification

Meta

Austin, TX • On-site, Remote

$178K/yr

Full-time

Posted 14 days ago

Meta rating

7.8

Company rating: 7.8 out of 10

Based on 45 frontline employees who took The Breakroom Quiz

136th of 242 rated software companies

Job description

Meta's Infrastructure Silicon team is seeking a Staff ASIC Design Verification Engineer to lead verification strategy and execution for custom silicon powering Meta's data center infrastructure. In this role, you will architect and drive end-to-end verification of complex IP blocks and SoCs designed for AI/ML acceleration, networking, and storage workloads. You will define scalable UVM-based verification environments, establish coverage closure methodologies, and partner with design, emulation, and post-silicon validation teams to ensure first-pass silicon success across Meta's infrastructure ASIC portfolio.
ASIC Engineer, Power Management Design Verification Responsibilities:
  • Define and implement IP/SoC verification plans, build verification test benches to enable IP/sub-system/SoC level verification
  • Develop functional tests based on the verification test plan
  • Drive design verification to closure based on defined verification metrics on the test plan, functional, and code coverage
  • Debug, root-cause and resolve functional failures in the design, partnering with the design team
  • Collaborate with cross-functional teams like Design, Model, Emulation, and silicon validation teams towards ensuring the highest design quality
  • Develop and drive continuous design verification improvements using the latest verification methodologies, tools, and technologies from the industry

Minimum Qualifications:
  • Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience
  • Bachelor's degree in Computer Science, Computer Engineering, a relevant technical field, or equivalent practical experience
  • 8+ years of hands-on experience in SystemVerilog/UVM methodology and/or C/C++ based verification
  • 8+ years of experience in IP/sub-system and/or SoC level verification based on SystemVerilog UVM/OVM based methodologies
  • Experience in one or more of the following areas, along with functional verification, SV assertions, formal, and emulation
  • Experience in EDA tools and scripting (Python, TCL, Perl, Shell) used to build tools and flows for verification environments
  • Experience in architecting and implementing design verification infrastructure and executing the full verification cycle
  • Familiarity with power management verification concepts

Preferred Qualifications:
  • Experience verifying compute, memory, or interconnect subsystems within AI/ML accelerator or data center networking SoCs
  • Experience with ARM, RISC-V, or GPU-based subsystem verification at the IP or full-chip level
  • Familiarity with host and system-level software stacks as they relate to hardware functional verification and stimulus generation
  • Experience with chiplet-based architectures and package-level integration verification methodologies

About Meta:
Meta builds technologies that help people connect, find communities, and grow businesses. When Facebook launched in 2004, it changed the way people connect. Apps like Messenger, Instagram and WhatsApp further empowered billions around the world. Now, Meta is moving beyond 2D screens toward immersive experiences like augmented and virtual reality to help build the next evolution in social technology. People who choose to build their careers by building with us at Meta help shape a future that will take us beyond what digital connection makes possible today—beyond the constraints of screens, the limits of distance, and even the rules of physics.
Meta is proud to be an Equal Employment Opportunity and Affirmative Action employer. We do not discriminate based upon race, religion, color, national origin, sex (including pregnancy, childbirth, or related medical conditions), sexual orientation, gender, gender identity, gender expression, transgender status, sexual stereotypes, age, status as a protected veteran, status as an individual with a disability, or other applicable legally protected characteristics. We also consider qualified applicants with criminal histories, consistent with applicable federal, state and local law. Meta participates in the E-Verify program in certain locations, as required by law. Please note that Meta may leverage artificial intelligence and machine learning technologies in connection with applications for employment.
Meta is committed to providing reasonable accommodations for candidates with disabilities in our recruiting process. If you need any assistance or accommodations due to a disability, please let us know at accommodations-ext@meta.com.
$178,000/year to $250,000/year + bonus + equity + benefits
Individual compensation is determined by skills, qualifications, experience, and location. Compensation details listed in this posting reflect the base hourly rate, monthly rate, or annual salary only, and do not include bonus, equity or sales incentives, if applicable. In addition to base compensation, Meta offers benefits. Learn more about benefits at Meta.

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