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Netlist Jobs (NOW HIRING)

SoC Physical Design Engineer, PnR

San Jose, CA · On-site

$159K - $164K/yr

In this visible role, you will be directly responsible for the physical implementation of design partition(s) (from netlist to tapeout) for a highly complex SOC utilizing innovative process ...

In this visible role, you will be directly responsible for the physical implementation of design partition(s) (from netlist to tapeout) for a highly complex SOC utilizing innovative process ...

SoC Physical Design Engineer, PnR

San Jose, CA · On-site

$159K - $164K/yr

In this visible role, you will be directly responsible for the physical implementation of design partition(s) (from netlist to tapeout) for a highly complex SOC utilizing innovative process ...

Physical Design Engineer

Sunnyvale, CA · On-site

$162K - $166K/yr

JD: • 10+ years of hands-on experience for block level Implementation activities(Netlist to GDS II and Signoff). • Experience in 7nm or 5nm and below tech nodes. • Experience in Cadence tools ...

SoC Physical Design Engineer, PnR

San Diego, CA · On-site

$142.30 - $263.30/hr

  • Medical

  • Dental

  • Retirement

Complete netlist to GDS2 implementation for partition(s) meeting schedule and design goals. * Timing, physical and electrical verification, and driving the signoff closure for the partitions.

SoC Physical Design Engineer, PnR

Beaverton, OR · On-site

$141K - $145K/yr

In this visible role, you will be directly responsible for the physical implementation of design partition(s) (from netlist to tapeout) for a highly complex SOC utilizing innovative process ...

In this visible role, you will be directly responsible for the physical implementation of design partition(s) (from netlist to tapeout) for a highly complex SOC utilizing innovative process ...

STA Engineer

Santa Clara, CA · On-site

$117K - $160K/yr

Experience in Synthesis, Logical Equivalence Checking (LEC) (RTL-to-Netlist and Netlist-to-Netlist). * Understanding of SOC clocking and reset methodology and implementation. * Scripting skills in ...

... netlist checks • Clock Tree Analysis and Optimization • ECO methods for functional and timing fixes • Managing design goals and tradeoffs in power, performance, and area Preferred ...

End-to-end DFT lifecycle experience, from RTL/netlist through silicon debug * Strong debugging skills, attention to detail, and sense of ownership * Excellent verbal and written communication skills ...

... netlist checks to validate functionality and netlist quality Experience implementing ECOs for functionality and timing Experience with one or more of: reset domain, multi-clock domain, multi-power ...

STA Engineer

Santa Clara, CA · On-site

$116K - $159K/yr

Experience in Synthesis, Logical Equivalence Checking (LEC) (RTL-to-Netlist and Netlist-to-Netlist). * Understanding of SOC clocking and reset methodology and implementation. * Scripting skills in ...

Completing netlist to GDS2 implementation for partition(s) meeting schedule and design goals. * Timing, physical and electrical verification, and driving the signoff closure for the partitions.

Principal SoC DFT Engineer

San Jose, CA · On-site

$159K - $296K/yr

This is a highly execution-driven role requiring end-to-end ownership of DFT insertion, verification, DRC closure, and test coverage closure from RTL/netlist through post-silicon debug. As a senior ...

SoC Physical Design Engineer, PnR

San Jose, CA

$150K - $277K/yr

  • Medical

  • Dental

  • Retirement

In this visible role, you will be directly responsible for the physical implementation of design partition(s) (from netlist to tapeout) for a highly complex SOC utilizing innovative process ...

Showing results 41-60

Netlist information

See salary details

$54K

$126.8K

$158K

How much do netlist jobs pay per year?

As of Aug 19, 2026, the average yearly pay for netlist in the United States is $126,844.00, according to ZipRecruiter salary data. Most workers in this role earn between $109,500.00 and $144,500.00 per year, depending on experience, location, and employer.

What is a netlist?

A Netlist is a description of the connectivity between electronic components within a circuit, typically represented in a text format for use in electronic design automation (EDA) tools. It lists all the components (like resistors, transistors, and capacitors) and specifies how their terminals are interconnected. Netlists are essential because they serve as a bridge between the schematic design and the physical layout of a circuit, enabling simulation, verification, and manufacturing processes. By providing a standardized way to represent circuit connections, netlists help ensure accuracy and consistency throughout the design and production phases.

What are the key skills and qualifications needed to thrive as a netlist engineer?

To excel as a Netlist Engineer, you need a solid background in electronic engineering, proficiency in digital circuit design, and experience with netlist generation and verification. Familiarity with EDA tools such as Cadence, Synopsys, or Mentor Graphics, as well as scripting languages like TCL or Python, is commonly required. Attention to detail, problem-solving abilities, and effective communication are crucial soft skills that set top performers apart. These competencies are vital for ensuring accurate circuit representations, streamlining the design process, and facilitating collaboration within engineering teams.

What are some common challenges faced by engineers working with netlists in electronic design automation (EDA) projects?

Engineers working with netlists often encounter challenges related to ensuring accuracy and consistency between different stages of the design process, such as schematic capture and physical layout. Managing large and complex netlists can make it difficult to quickly identify connectivity errors or mismatches, which can impact the functionality and timing of the final product. Collaboration with circuit designers, layout engineers, and verification teams is crucial to resolve discrepancies and streamline workflows. Familiarity with EDA tools, scripting, and version control systems can help engineers effectively manage these challenges.

What is the difference between Netlist vs PCB Designer?

AspectNetlistPCB Designer
Primary RoleCreates netlists that define electrical connections in a circuitDesigns printed circuit boards, including layout and component placement
Skills & CertificationsKnowledge of circuit design, electrical engineering, and CAD toolsProficiency in PCB design software, electrical engineering, and layout standards
Work EnvironmentTypically in engineering or design teams, using CAD and simulation toolsDesign studios, engineering firms, or manufacturing environments
Industry UsageUsed in electronics, hardware development, and circuit designUsed in electronics manufacturing, hardware development, and product design

While both roles are integral to electronics design, a Netlist focuses on defining electrical connections, whereas a PCB Designer creates the physical layout of the circuit board. They often collaborate closely in the product development process.

More about Netlist jobs

What cities are hiring for Netlist jobs?

Cities with the most Netlist job openings:

What states have the most Netlist jobs?

States with the most job openings for Netlist jobs include:

What job categories do people searching Netlist jobs look for?

The top searched job categories for Netlist jobs are:

Infographic showing various Netlist job openings in the United States as of August 2026, with employment types broken down into 76% Full Time, and 24% Contract. Highlights an 88% In-person, 6% Hybrid, and 6% Remote job distribution, with an average salary of $126,844 per year, or $61 per hour.

Principal Engineer, Physical Design

InnoPhase IoT

San Diego, CA

$144K - $148K/yr

Full-time

Re-posted 9 days ago


Job description

Overview of Role

As a Physical Design Principal Engineer, you will be responsible for the entire SOC implementation and verification flow from RTL-to-GDS that includes floorplan, place and route, CTS, STA, PV/EMIR/Noise/SigEM cleanup and signoff on lower power SoC. You will be joining a team of engineers dedicated to pushing the envelope for a leading fabless wireless semiconductor platform company specializing in extreme low power wireless radio solutions.

Location

  • San Diego or San Jose, CA

Responsibilities

  • Complete entire physical implementation of the block and chip level
  • Perform synthesis and physical implementation steps - synthesis, floor-planning, power delivery, place&route, timing noise, physical verification, IR/RV.
  • Collaborate with the SOC design team to drive architectural feasibility studies, develop timing, power, and area design targets, and explore RTL/design tradeoffs
  • Analyze the quality of the floorplan and Customized Clock tree structure and Place & Route
  • Implement ECOs for timing closure
  • Signal EM/Noise and Power IR/EM analysis and fix
  • DRC/LVS/ERC/ANTENNA analysis and clean up
  • Timing verification and signoff
  • Physical verification and sign off

Minimum Qualifications

  • Master's degree or above in electrical/computer science engineering with 10+ years of industry experience, or bachelor's degree in electrical/computer science engineering plus 15+ years of industry experience
  • Strong experience in Power/Ground grids, Partitioning, Timing ECO implementation, and physical verification.
  • The entire SOC implementation and verification flow from RTL-to-GDS that includes fullchip floorplan, place and route, CTS, and layout verification signoff on lower power SoC
  • Netlist (or RTL)-GDS physical implementation experience
  • In depth knowledge of major EDA tools/design flows
  • Strong Cadence experience/background
  • Experience with TSMC N22 or below technology
  • Experience in chip integration and signoff
  • Experience in Perl/TCL language programming

Preferred Qualifications

  • Strong experience in Low-power implementation methodology
  • Strong experience in Advanced timing signoff methodology
  • Knowledge of DFT (BSCAN, MBIST, SCAN) and understanding of their impact on physical design flows
  • Able to independently complete Netlist-GDS P&R, signoff task
  • Proven record in multi-million gate design production tapeouts