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About the Role

The CEG NAG (Networking Architecture Group) is Intel's premier team focused on defining the future of high-performance networking silicon. Our team architects next-generation networking solutions that enable hyperscale data centers, cloud infrastructure, and AI workloads to achieve unprecedented performance and efficiency. We specialize in IPU/DPU platforms, advanced packet processing architectures, and programmable networking technologies that form the backbone of modern distributed computing systems.

We are seeking a Senior SoC Chiplet Architect to define and lead the architecture strategy for multi-generation, chiplet-based SoC platforms targeting next-generation data center workloads.

This role is responsible for chiplet partitioning, die-to-die (D2D) interconnect architecture, and system-level tradeoff analysis across performance, power, area (PPA), cost/yield, and software complexity. You will drive modular, scalable SoC design approaches, including cross-chiplet coherency, system infrastructure (boot/reset/telemetry), and RAS/security architectures across multi-die systems.

What You'll Do

Key responsibilities will include but not limited to:

Chiplet Architecture Strategy and Roadmap
1. Define the monolithic vs. chiplet decision framework and multi-generation roadmap, incorporating reticle scaling limits, yield economics, modularity, and portfolio reuse strategy
2. Lead architecture studies for 2-die / 3-die / multi-chiplet scaling (compute + I/O/network + memory/accelerators), including partition boundaries, SKU scalability, and future-proof modular upgrades
3. Produce executive-ready architecture options and recommendations for leadership decisions (build/partner/standardize)

Chiplet Partition, Resource Scaling, and System Topology
1. Drive functional partitioning across chiplets (compute, networking/I/O, accelerators, memory controllers, security/management), balancing PPA, D2D bandwidth/latency, validation complexity, and product flexibility
2. Define scalable system resource models (e.g., memory channels, PCIe lanes, pipeline scaling) and how these scale with chiplet count and topology
3. Specify any required logic / gaskets and integration constraints to enable modular assembly and consistent SW-visible behavior

Die-to-Die (D2D) Interconnect Architecture and QoS
1. Architect D2D communication for high bandwidth, low latency, and reliability across chiplets; define link budgets and requirements for bandwidth, latency, error handling, and flow control
2. Define inter-chiplet QoS mechanisms (e.g., arbitration, prioritization, isolation) and ensure the architecture supports workload-driven traffic patterns at scale
3. Align D2D choices with industry standardization direction (where applicable) and ensure project-specific needs can be encapsulated cleanly

Chiplet System Infrastructure: Power, Clock/Reset, Boot, telemetry
1. Define coordinated power delivery and power management flows across chiplets (telemetry, quiescence, package states, throttling), including system-level sequencing and corner cases
2. Architect clocking and reset distribution (reference clock delivery, local PLL strategies, reset sequencing, debug/manufacturing hooks) and ensure robust bring-up across all dies
3. Drive the chiplet-aware boot and early firmware architecture (e.g., parallel boot considerations, coordinated reset control) in partnership with FW/platform teams

RAS, Debug, and Observability Across Chiplets
1. Define cross-chiplet error reporting, containment, and recovery policies, including consistent crashdump, telemetry access, and actionable observability for post-silicon debug
2. Specify debug/trace infrastructure assumptions to ensure chiplet partitioning does not compromise lab efficiency or field diagnosability

Quantitative Trade Off Studies
1. Lead quantitative trade studies across performance, power, area, cost/yield, and schedule; identify bottlenecks and propose architecture-level mitigations
2. Partner with packaging/manufacturing stakeholders for trade-off comparisons (e.g., explicitly tracking whether packaging overheads are included in a given analysis)

Cross-Functional Technical Leadership
1. Drive alignment across architecture, RTL, DV, FW/SW, packaging, and platform teams; lead reviews, challenge assumptions, and converge on clear architectural decisions
2. Work with other architects and contribute reusable patterns/checklists for chiplet-based SoC infrastructure

Behavioral traits that we are looking for:

• Strategic vision: Defines long-term chiplet architecture direction across product lines
• Complex decision-making: Evaluates multidimensional tradeoffs (PPA, cost, schedule, risk)
• Influence at scale: Drives alignment across organizations without direct authority
• Systems-level thinking: Understands full-stack implications (hardware, firmware, software, manufacturing)
• Executive communication: Translates complex architecture into clear recommendations
• Collaboration: Partners effectively across architecture, packaging, and platform teams
• Ownership mindset: Leads from concept through productization
• Adaptability: Navigates evolving standards and rapidly advancing technologies

Intel invests in our people and offers a complete and competitive package of benefits employees and their families through every stage of life.

See Intel Benefitsfor more details.

Qualifications:

Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

Note:

For information on Intel's immigration sponsorship guidelines, please see

Intel U.S. Immigration Sponsorship Information

Minimum Qualifications and Experience:

Batchelor's degree in Electrical Engineering, Computer Engineering, or in a STEM related Field of Study.

You must have 7 + years of experience in the following:

• SoC/system architecture, including end-to-end architecture definition from requirements to silicon execution
• Experience with multi-die / chiplet partitioning and the associated system implications (D2D, boot/reset, cross-domain QoS, debug)
• Run architecture trade-off studies and communicate decisions crisply to senior technical and business stakeholders

Preferred Qualifications and Experience:

• Familiarity with industry direction on chiplet interoperability and standardization and/or participation in ecosystem discussions
• Hands-on experience with system bring-up flows and architecture-driven debug/telemetry planning across complex SoCs
• Architecture fundamentals in interconnects/fabrics, memory subsystem behavior, performance modeling, and PPA tradeoffs
• Experience building or consuming cost/yield models for architectural decision-making (including explicitly scoping what cost elements are included)

Join us in building a brighter future through technology innovation!

Job Type:Experienced HireShift:Shift 1 (United States of America)Primary Location: US, California, Santa ClaraAdditional Locations:US, Arizona, Phoenix, US, California, Folsom, US, Colorado, Fort Collins, US, Oregon, Hillsboro, US, Texas, AustinBusiness group:The Central Engineering Group (CEG) is Intel's data-driven organization that builds scalable engineering solutions across three pillars: Product Enablement (IP, tools, and methodologies), Custom ASIC (leveraging existing IP for custom silicon), and Foundry Enablement (supporting top customers and validating technologies). The team focuses on customer-driven, end-to-end solutions with short development cycles to deliver measurable business impact across Intel's product and foundry businesses.Posting Statement:All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.Position of TrustN/ABenefits

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel.

Annual Salary Range for jobs which could be performed in the US: $164,470.00-269,100.00 USDThe range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.The application window for this job posting is expected to end by 07/31/2026

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ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.