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Mask Layout Engineer Jobs (NOW HIRING)

Pacer Group

Analog Layout Engineer

Irvine, CA · On-site

$216.80K/yr

Analog Layout Engineer Job Location: Irvine/San Jose (CA), Minneapolis (MN), Phoenix/Chandler (AZ ... Utilizing advanced CAD tools and mask design knowledge to deliver correct and robust layout that ...

Micron Technology

Sr Layout Engineer, DDEG

Boise, ID · On-site

As a Layout Engineer in DDEG, you will translate schematics into manufacturable layouts that meet ... Coordinate with global partners to meet predictable schedules and support tapeout/mask generation ...

Apple

RFIC Layout Engineer

Austin, TX · On-site

As an RFIC Layout Engineer, you will address intriguing daily layout challenges, collaborate with skilled RFIC design and layout teams, and continuously improve products to surpass previous ...

Micron

Sr Layout Engineer, DDEG

Boise, ID · On-site

As a Layout Engineer in DDEG, you will translate schematics into manufacturable layouts that meet ... Coordinate with global partners to meet predictable schedules and support tapeout/mask generation ...

Micron Technology

Sr Layout Engineer, DDEG

Boise, ID · On-site

As a Layout Engineer in DDEG, you will translate schematics into manufacturable layouts that meet ... Coordinate with global partners to meet predictable schedules and support tapeout/mask generation ...

Neuralink

Analog IC Layout Engineer

Fremont, CA

As an Analog IC Layout Engineer, your responsibilities will include: * Crafting state-of-the-art ... Physical verification of custom IC mask layouts (LVS, DRC, ERC) Required Qualifications: * 2+ years ...

Apple

RFIC Layout Engineer

Irvine, CA · On-site

$134.80K - $245.80K/yr

Capability to lead other layout engineers for top-level integration. Scripting skills in PERL or SKILL are a plus. Minimum Qualifications BS and 3+ years of relevant industry experience. Good ...

Apple

RFIC Layout Engineer

Irvine, CA

$42.23 - $75.14/hr

Capability to lead other layout engineers for top-level integration. Scripting skills in PERL or SKILL are a plus. Minimum Qualifications 8+ year minimum related experience required Good ...

Apple

RFIC Layout Engineer

Irvine, CA

$134.80K - $245.80K/yr

Capability to lead other layout engineers for top-level integration. Scripting skills in PERL or SKILL are a plus. Minimum Qualifications BS and 3+ years of relevant industry experience. Good ...

Apple

RFIC Layout Engineer

Irvine, CA · On-site

$163.30K - $290.10K/yr

Top-level layout integration and verification, schedule management.","responsibilities":"As a RF layout engineer, you will be responsible for: Detailed transistor-level layout of RF and analog ...

Apple

RFIC Layout Engineer

Irvine, CA

$163.30K - $290.10K/yr

Top-level layout integration and verification, schedule management.","responsibilities":"As a RF layout engineer, you will be responsible for: Detailed transistor-level layout of RF and analog ...

Apple

RFIC Layout Engineer

Irvine, CA

$134.80K - $245.80K/yr

Capability to lead other layout engineers for top-level integration. Scripting skills in PERL or SKILL are a plus. Minimum Qualifications BS and 3+ years of relevant industry experience. Good ...

Apple

RFIC Layout Engineer

Austin, TX · On-site

As an RFIC Layout Engineer, you will address intriguing daily layout challenges, collaborate with skilled RFIC design and layout teams, and continuously improve products to surpass previous ...

Apple

RFIC Layout Engineer

Irvine, CA

$42.23 - $75.14/hr

Capability to lead other layout engineers for top-level integration. Scripting skills in PERL or SKILL are a plus. Minimum Qualifications 8+ year minimum related experience required Good ...

Apple

RFIC Layout Engineer

Irvine, CA

$42.23 - $75.14/hr

Capability to lead other layout engineers for top-level integration. Scripting skills in PERL or SKILL are a plus. Minimum Qualifications 8+ year minimum related experience required Good ...

Apple

RFIC Layout Engineer

Irvine, CA

$163.30K - $290.10K/yr

Top-level layout integration and verification, schedule management.","responsibilities":"As a RF layout engineer, you will be responsible for: Detailed transistor-level layout of RF and analog ...

Apple

RFIC Layout Engineer

Austin, TX

$115.71K - $203K/yr

As an RFIC Layout Engineer, you will address intriguing daily layout challenges, collaborate with skilled RFIC design and layout teams, and continuously improve products to surpass previous ...

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Mask Layout Engineer information

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$45K

$120.8K

$185.5K

How much do mask layout engineer jobs pay per year?

As of Jun 1, 2026, the average yearly pay for mask layout engineer in the United States is $120,849.00, according to ZipRecruiter salary data. Most workers in this role earn between $90,000.00 and $144,000.00 per year, depending on experience, location, and employer.

What is a Mask Layout Engineer job?

A Mask Layout Engineer is responsible for designing the physical layout of integrated circuits (ICs) based on schematic designs. They ensure that the layout meets design specifications, electrical performance criteria, and manufacturability constraints. This involves working with design rules, placement, routing, and verification tools to optimize performance and minimize errors. Mask Layout Engineers collaborate closely with circuit design teams, process engineers, and foundry teams to ensure that the final design can be successfully fabricated. Their work is critical in semiconductor manufacturing, impacting chip performance, size, and power efficiency.

What are the key skills and qualifications needed to thrive in the Mask Layout Engineer position, and why are they important?

A Mask Layout Engineer needs a solid background in semiconductor physics, microelectronics, and integrated circuit (IC) design, often supported by a relevant engineering degree. Proficiency with Electronic Design Automation (EDA) tools such as Cadence Virtuoso, Mentor Graphics, or Synopsys is typically required, and familiarity with industry standards like DRC/LVS checking is valuable. Strong attention to detail, problem-solving skills, and clear communication are important soft skills for collaborating with design and verification teams. These competencies are essential to ensure accurate, reliable IC layouts that meet stringent design and manufacturing specifications.

What does a typical day look like for a Mask Layout Engineer?

A typical day for a Mask Layout Engineer involves translating circuit schematics into precise physical layouts using specialized software, running design rule checks (DRC) and layout versus schematic (LVS) verifications, and collaborating closely with circuit designers to resolve any issues or challenges. You’ll spend a significant portion of your time ensuring that layouts meet manufacturing process constraints and optimizing for performance and manufacturability. Mask Layout Engineers often work as part of a larger IC design team, interacting regularly with other engineers, project managers, and sometimes foundry partners. This role offers opportunities to deepen your technical skills and advance towards senior layout, design, or project leadership positions over time.
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Mask Layout Engineer jobs near you
Infographic showing various Mask Layout Engineer job openings in the United States as of May 2026, with employment types broken down into 23% Full Time, 31% Part Time, and 46% Contract. Highlights an 78% Physical, 19% Hybrid, and 3% Remote job distribution, with an average salary of $120,849 per year, or $58.1 per hour.
Analog Layout Engineer

Analog Layout Engineer

Pacer Group

Irvine, CA • On-site

$216.80K/yr

Contractor

Posted 18 days ago

Job description

Job Title: Analog Layout Engineer
Job Location: Irvine/San Jose (CA), Minneapolis (MN), Phoenix/Chandler (AZ)
Job Duration: 3 Months, Contract to Hire
 
Job Responsibilities: 
  • Lead layout team in completing complex layout for analog/mixed-signal circuits in deep submicron CMOS technologies
  • Be a great role model, by inspiring and motivating team, and Establishing Effective Organizational Structure and Communication Protocols. Able to Delegate and Empower team along with Effective Time Management.
  • Working with the circuit designer or Layout-Lead to plan/schedule work and negotiate any layout trade-offs as needed
  • Reviewing and analyzing floorplans and complex circuits with circuit designers
  • Running complete set of design verification tools available on AMS blocks
  • Interpreting LVS, DRC and ERC reports to find the fastest way to complete layout
  • Utilizing advanced CAD tools and mask design knowledge to deliver correct and robust layout that meet stringent matching performance, area, and power requirements
Qualifications:
  •  10+ years of experience in analog/mixed-signal layout design of deep submicron CMOS circuits and at least 3+ years of recent experience on advance nodes including FinFET technologies
  • Experience with and knowledge of analog/mixed-signal IP (e.g., SERDES PHY, transmitter and receiver, PLL, DDR PHY, ADCs, DACs, LDOs, etc.)
  • Experience leading complex layout macros during the full design cycle from floorplan analysis to completion of physical design verification
  • Great understanding of CAD flows and tools related to analog/mixed-signal layout design
  • Experience crafting well-matched, low noise, and low power analog blocks consisting of transistors, resistors, capacitors, pad IO's, ESD structures, etc.
  • High level of proficiency in custom, as well as standard cell-based, floorplanning and hierarchical layout assembly
  • Must understand issues of IR drop, RC delay, electro-migration, self-heating and coupling capacitance
  • Must recognize failure prone circuit and layout structures, have experience with analog and DFM standard methodologies, and enthusiastically work with circuit designer or layout lead for the best approach to problems
  • High level of proficiency in interpretation of CALIBRE DRC, ERC, LVS, etc., reports
  • Knowledge of CADENCE or MENTOR GRAPHICS layout tools.
  • Excellent interpersonal skills and able to work with remote teams
Mandatory Skills:
  • Synopsys/Cadence Analog Layout Tools (Preference: 5)
  • Memory design and layout (Preference: 5)
  • Python (Preference: 2)