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Entry Level Mask Layout Engineer Jobs (NOW HIRING)

Texas Instruments

RET Layout/Mask Engineer

Dallas, TX · On-site

As a Resolution Enhancement Techniques (RET) Layout Engineer, you will architect new TI products ... Mask design. Preferred qualifications: * Hands-on experience in design or PDK development with ...

Neuralink

Analog IC Layout Engineer

Fremont, CA

As an Analog IC Layout Engineer, your responsibilities will include: * Crafting state-of-the-art ... Physical verification of custom IC mask layouts (LVS, DRC, ERC) Required Qualifications: * 2+ years ...

Apple

RFIC Layout Engineer

Irvine, CA

$43.07 - $76.64/hr

Capability to lead other layout engineers for top-level integration. Minimum Qualifications 8+ year minimum related experience required Good understanding of RC delay, electromigration, and coupling.

Apple

RFIC Layout Engineer

Irvine, CA

$43.07 - $76.64/hr

Capability to lead other layout engineers for top-level integration. Minimum Qualifications 8+ year minimum related experience required Good understanding of RC delay, electromigration, and coupling.

Apple

RFIC Layout Engineer

Austin, TX · On-site

As an RFIC Layout Engineer, you will address intriguing daily layout challenges, collaborate with skilled RFIC design and layout teams, and continuously improve products to surpass previous ...

Apple

RFIC Layout Engineer

Irvine, CA

$43.07 - $76.64/hr

Capability to lead other layout engineers for top-level integration. Minimum Qualifications 8+ year minimum related experience required Good understanding of RC delay, electromigration, and coupling.

Micron Technology

Layout Engineer, DEG

Boise, ID · On-site

Our layout engineering team drives the physical design foundations behind Micron's industry-leading memory technologies. We work closely across global design, CAD, and verification groups, solving ...

Apple

RFIC Layout Engineer

Austin, TX

$118K - $207K/yr

As an RFIC Layout Engineer, you will address intriguing daily layout challenges, collaborate with skilled RFIC design and layout teams, and continuously improve products to surpass previous ...

Micron

Layout Engineer, DEG

Boise, ID · On-site

Our layout engineering team drives the physical design foundations behind Micron's industryleading memory technologies. We work closely across global design, CAD, and verification groups, solving ...

Apple

RFIC Layout Engineer

Austin, TX

$118K - $207K/yr

As an RFIC Layout Engineer, you will address intriguing daily layout challenges, collaborate with skilled RFIC design and layout teams, and continuously improve products to surpass previous ...

Neuralink

Analog IC Layout Engineer

Fremont, CA · On-site

$83K - $139K/yr

As an Analog IC Layout Engineer, your responsibilities will include: * Crafting state-of-the-art ... Physical verification of custom IC mask layouts (LVS, DRC, ERC) Required Qualifications: * 2+ years ...

Apple

RFIC Layout Engineer

Austin, TX

$118K - $207K/yr

As an RFIC Layout Engineer, you will address intriguing daily layout challenges, collaborate with skilled RFIC design and layout teams, and continuously improve products to surpass previous ...

Micron Technology

SR Layout Engineer, DEG

Boise, ID · On-site

We're looking for a Layout Engineer who will play a key role in building high-quality physical designs for our DRAM technologies. As an IP layout engineer, you will work with a dedicated and ...

Micron

SR Layout Engineer, DEG

Boise, ID

We're looking for a Layout Engineer who will play a key role in building highquality physical designs for our DRAM technologies. As an IP layout engineer, you will work with a dedicated and ...

TSMC

Layout Engineer (7753)

San Jose, CA · On-site

$120K - $167K/yr

Layout Engineer Coordinate design changes and design fitting issues, and other technical data to ensure customer's design can fit TSMC's production flow and procedures. Specific tasks will include ...

TSMC

Layout Engineer (7752)

San Jose, CA · On-site

$120K - $160K/yr

Layout Engineer Coordinate the design changes, design fitting issues, and other technical data to ensure customers' designs can fit TSMC's production flow and procedures. Specific tasks include but ...

TSMC

Layout Engineer (7752)

San Jose, CA · On-site

$120K - $160K/yr

Layout Engineer Coordinate the design changes, design fitting issues, and other technical data to ensure customers' designs can fit TSMC's production flow and procedures. Specific tasks include but ...

Micron

Layout/Mask Designer

Boise, ID · On-site

May telecommute part-time. Employer will accept a Bachelor's degree in Electrical Engineering ... Layout principles for analog and digital blocks, including symmetry, matching, shielding, and ...

PDF Solutions

Senior Layout Extraction Engineer

Midvale, UT · On-site +1

$120K - $160K/yr

The Layout (FIRE) Extraction Engineer is an organized and highly motivated team player with strong ... mask fabrication and design rules (DRC) o Software/Tool Proficiency · Experience with OPC/Mask ...

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Entry Level Mask Layout Engineer information

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$40.5K

$86.4K

$142.5K

How much do entry level mask layout engineer jobs pay per year?

As of Jul 14, 2026, the average yearly pay for entry level mask layout engineer in the United States is $86,381.00, according to ZipRecruiter salary data. Most workers in this role earn between $65,000.00 and $103,500.00 per year, depending on experience, location, and employer.
What are the most commonly searched types of Mask Layout Engineer jobs? The most popular types of Mask Layout Engineer jobs are:
Entry Level Mask Layout Engineer jobs near you
RET Layout/Mask Engineer

RET Layout/Mask Engineer

Texas Instruments

Dallas, TX • On-site

Other

Posted 29 days ago

Texas Instruments rating

8.1

Company rating: 8.1 out of 10

Based on 86 frontline employees who took The Breakroom Quiz

41st of 142 rated electronics manufacturers

Job description

Change the world. Love your job. 
Texas Instruments is in an exciting era of growth and innovation, and our Advanced Technology Development (ATD) organization is at the center of it - developing the 28nm process technologies that will define TI's next generation of analog and embedded processing capabilities. As part of ATD, you won't just support production - you'll create the technology that makes it possible. Our engineers are working at the leading edge of computational lithography, Resolution Enhancement Techniques, and advanced process integration, solving the fundamental patterning and process challenges that determine whether a 28nm technology can be manufactured at scale and at yield. The work done in ATD directly enables fabs that will manufacture tens of millions of analog and embedded processing chips every day - supporting customer demand for decades to come. We're committed to responsible, sustainable semiconductor manufacturing and to building a diverse, technically excellent team that drives meaningful impact across the industry. In this role, you'll work at the intersection of fundamental research and high-volume manufacturing, turning process innovations into production-ready technologies that power electronics everywhere.

As a Resolution Enhancement Techniques (RET) Layout Engineer, you will architect new TI products and make our customers' visions a reality. You will define, design, model, implement, and document analog, digital, and RF integrated circuits (ICs). 

Responsibilities will include, but are not limited to: 

  • Create layouts for setup, evaluation, and monitor of lithography/etch wafer processes.
    • Work with fabrication process engineering and integration teams to determine specifications.
    • Use design rules and/or existing layouts to create/modify test features.
    • Maintain a list of measurement coordinate locations.
    • Support and interaction for all fabs and technologies required.
  • Create layouts for OPC development/monitor.
    • Work with other RET engineers on layout and floor plan of test reticles for OPC model calibration and recipe development.
    • Work with RET engineers to layout scribe modules for OPC model calibration/testing.
  • Create layouts for reticle measurement and disposition.
    • Work with other RET engineers and the PDK team to define specifications.
    • Maintain a list of measurement coordinate locations.
    • Work with RET, scribe, and design teams to create rules for layout placement.
  • Develop and implement automation for producing layouts.
Why TI?
  • Engineer your future. We empower our employees to truly own their career and development. Come collaborate with some of the smartest people in the world to shape the future of electronics.
  • We're different by design. Diverse backgrounds and perspectives are what push innovation forward and what make TI stronger. We value each and every voice, and look forward to hearing yours. Meet the people of TI
  • Benefits that benefit you. We offer competitive pay and benefits designed to help you and your family live your best life. Your well-being is important to us. Please find our country-specific benefits here

About Texas Instruments
Texas Instruments Incorporated (Nasdaq: TXN) is a global semiconductor company that designs, manufactures and sells analog and embedded processing chips for markets such as industrial, automotive, data center, personal electronics and communications equipment. At our core, we have a passion to create a better world by making electronics more affordable through semiconductors. This passion is alive today as each generation of innovation builds upon the last to make our technology more reliable, more affordable and lower power, making it possible for semiconductors to go into electronics everywhere. Learn more at TI.com.

Texas Instruments is an equal opportunity employer and supports a diverse, inclusive work environment. All qualified applicants will receive consideration for employment without regard to race, color, religion, creed, disability, genetic information, national origin, gender, gender identity and expression, age, sexual orientation, marital status, veteran status, or any other characteristic protected by federal, state, or local laws.

If you are interested in this position, please apply to this requisition.
TI does not make recruiting or hiring decisions based on citizenship, immigration status or national origin. However, if TI determines that information access or export control restrictions based upon applicable laws and regulations would prohibit you from working in this position without first obtaining an export license, TI expressly reserves the right not to seek such a license for you and either offer you a different position that does not require an export license or decline to move forward with your employment.

Minimum qualifications:

  • Bachelors in Electrical Engineering, Physics, Computer Science, Chemistry or related degree
  • Proficiency with EDA layout tools (Cadence suite, Synopsys, etc.) and scripting (e.g., Python, SKILL, Perl)
  • 5+ years of experience in Layout/Mask design.

Preferred qualifications:

  • Hands-on experience in design or PDK development with direct experience at a semiconductor company
  • Excellent problem-solving, analytical, and communication skills for cross-team collaboration
  • Experience working with PG flows
  • Strong lithography knowledge
  • OPC experience

What Texas Instruments employees say

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About Texas Instruments

Sourced by ZipRecruiter

As a global semiconductor company, we design, manufacture, test and sell analog and embedded processing chips to nearly 100,000 customers. Our products enable electronics everywhere and in things you experience every day - from health care, smart homes and connected cars to drones, smart phones and more. Our passion to create a better and more sustainable world by making electronics more affordable through semiconductors drives us to make our technology smaller, more efficient, more reliable and more affordable.

Industry

Semiconductor and electronic component manufacturing

Company size

10,000+ Employees

Headquarters location

Dallas, TX, US

Year founded

1930

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