As a Resolution Enhancement Techniques (RET) Layout Engineer, you will architect new TI products ... Mask design. Preferred qualifications: * Hands-on experience in design or PDK development with ...
As a Resolution Enhancement Techniques (RET) Layout Engineer, you will architect new TI products ... Mask design. Preferred qualifications: * Hands-on experience in design or PDK development with ...
As an Analog IC Layout Engineer, your responsibilities will include: * Crafting state-of-the-art ... Physical verification of custom IC mask layouts (LVS, DRC, ERC) Required Qualifications: * 2+ years ...
As an Analog IC Layout Engineer, your responsibilities will include: * Crafting state-of-the-art ... Physical verification of custom IC mask layouts (LVS, DRC, ERC) Required Qualifications: * 2+ years ...
RFIC Layout Engineer
$43.07 - $76.64/hr
Capability to lead other layout engineers for top-level integration. Minimum Qualifications 8+ year minimum related experience required Good understanding of RC delay, electromigration, and coupling.
RFIC Layout Engineer
$43.07 - $76.64/hr
Capability to lead other layout engineers for top-level integration. Minimum Qualifications 8+ year minimum related experience required Good understanding of RC delay, electromigration, and coupling.
RFIC Layout Engineer
$43.07 - $76.64/hr
Capability to lead other layout engineers for top-level integration. Minimum Qualifications 8+ year minimum related experience required Good understanding of RC delay, electromigration, and coupling.
RFIC Layout Engineer
$43.07 - $76.64/hr
Capability to lead other layout engineers for top-level integration. Minimum Qualifications 8+ year minimum related experience required Good understanding of RC delay, electromigration, and coupling.
RFIC Layout Engineer
$43.07 - $76.64/hr
Capability to lead other layout engineers for top-level integration. Minimum Qualifications 8+ year minimum related experience required Good understanding of RC delay, electromigration, and coupling.
RFIC Layout Engineer
$43.07 - $76.64/hr
Capability to lead other layout engineers for top-level integration. Minimum Qualifications 8+ year minimum related experience required Good understanding of RC delay, electromigration, and coupling.
Layout Engineer, DEG
Boise, ID · On-site
Our layout engineering team drives the physical design foundations behind Micron's industry-leading memory technologies. We work closely across global design, CAD, and verification groups, solving ...
Layout Engineer, DEG
Boise, ID · On-site
Our layout engineering team drives the physical design foundations behind Micron's industry-leading memory technologies. We work closely across global design, CAD, and verification groups, solving ...
Position Overview We are seeking an experienced IC Layout Engineer to support a high-priority project and help address increased design workload. The ideal candidate will have strong custom IC layout ...
Position Overview We are seeking an experienced IC Layout Engineer to support a high-priority project and help address increased design workload. The ideal candidate will have strong custom IC layout ...
Layout Engineer, DEG
Boise, ID · On-site
Our layout engineering team drives the physical design foundations behind Micron's industryleading memory technologies. We work closely across global design, CAD, and verification groups, solving ...
Layout Engineer, DEG
Boise, ID · On-site
Our layout engineering team drives the physical design foundations behind Micron's industryleading memory technologies. We work closely across global design, CAD, and verification groups, solving ...
Analog IC Layout Engineer
South San Francisco, CA · On-site
$83K - $139K/yr
As an Analog IC Layout Engineer, your responsibilities will include: * Crafting state-of-the-art ... Physical verification of custom IC mask layouts (LVS, DRC, ERC) Required Qualifications: * 2+ years ...
Analog IC Layout Engineer
South San Francisco, CA · On-site
$83K - $139K/yr
As an Analog IC Layout Engineer, your responsibilities will include: * Crafting state-of-the-art ... Physical verification of custom IC mask layouts (LVS, DRC, ERC) Required Qualifications: * 2+ years ...
Microelectronics Layout & Process Design Kit (PDK) Engineer
Manhattan Beach, CA · On-site
$91K - $137K/yr
... Layout & Process Design Kit (PDK) Engineer for our Space Park Foundry Lab (SPF) located in ... Create Mask Layouts using Cadence Basic Qualifications: * Bachelor of Science in Electrical ...
Microelectronics Layout & Process Design Kit (PDK) Engineer
Manhattan Beach, CA · On-site
$91K - $137K/yr
... Layout & Process Design Kit (PDK) Engineer for our Space Park Foundry Lab (SPF) located in ... Create Mask Layouts using Cadence Basic Qualifications: * Bachelor of Science in Electrical ...
Microelectronics Layout & Process Design Kit (PDK) Engineer
Manhattan Beach, CA · On-site
$91K - $137K/yr
... Layout & Process Design Kit (PDK) Engineer for our Space Park Foundry Lab (SPF) located in ... Create Mask Layouts using Cadence Basic Qualifications: * Bachelor of Science in Electrical ...
Microelectronics Layout & Process Design Kit (PDK) Engineer
Manhattan Beach, CA · On-site
$91K - $137K/yr
... Layout & Process Design Kit (PDK) Engineer for our Space Park Foundry Lab (SPF) located in ... Create Mask Layouts using Cadence Basic Qualifications: * Bachelor of Science in Electrical ...
SR Layout Engineer, DEG
Boise, ID · On-site
We're looking for a Layout Engineer who will play a key role in building high-quality physical designs for our DRAM technologies. As an IP layout engineer, you will work with a dedicated and ...
SR Layout Engineer, DEG
Boise, ID · On-site
We're looking for a Layout Engineer who will play a key role in building high-quality physical designs for our DRAM technologies. As an IP layout engineer, you will work with a dedicated and ...
SR Layout Engineer, DEG
Boise, ID · On-site
We're looking for a Layout Engineer who will play a key role in building highquality physical designs for our DRAM technologies. As an IP layout engineer, you will work with a dedicated and ...
SR Layout Engineer, DEG
Boise, ID · On-site
We're looking for a Layout Engineer who will play a key role in building highquality physical designs for our DRAM technologies. As an IP layout engineer, you will work with a dedicated and ...
As an Electrical PCB Layout Engineer, you will own PCB layout execution in Altium from schematic ... Working knowledge of PCB fabrication and assembly processes, including DFM, DFA, DFT, solder-mask ...
As an Electrical PCB Layout Engineer, you will own PCB layout execution in Altium from schematic ... Working knowledge of PCB fabrication and assembly processes, including DFM, DFA, DFT, solder-mask ...
As an Electrical PCB Layout Engineer, you will own PCB layout execution in Altium from schematic ... Working knowledge of PCB fabrication and assembly processes, including DFM, DFA, DFT, solder-mask ...
Quick apply
As an Electrical PCB Layout Engineer, you will own PCB layout execution in Altium from schematic ... Working knowledge of PCB fabrication and assembly processes, including DFM, DFA, DFT, solder-mask ...
Photonic Integrated Circuit (PIC) Design Engineer
Sunnyvale, CA · On-site
$179K - $332K/yr
We need motivated engineers and scientists to spearhead developing new products. A range of ... PIC mask layout design expertise with 10 or more layers * Extensive characterization of ...
Photonic Integrated Circuit (PIC) Design Engineer
Sunnyvale, CA · On-site
$179K - $332K/yr
We need motivated engineers and scientists to spearhead developing new products. A range of ... PIC mask layout design expertise with 10 or more layers * Extensive characterization of ...
We need motivated engineers and scientists to spearhead developing new products. A range of ... PIC mask layout design expertise with 10 or more layers * Extensive characterization of ...
We need motivated engineers and scientists to spearhead developing new products. A range of ... PIC mask layout design expertise with 10 or more layers * Extensive characterization of ...
Layout Support Engineer
Andover, MA · On-site
As a Layout Engineer you will be responsible for creating layouts to the specifications of the engineering team, and to perform design checks and physical verification on RF Integrated Circuits (RFIC ...
Layout Support Engineer
Andover, MA · On-site
As a Layout Engineer you will be responsible for creating layouts to the specifications of the engineering team, and to perform design checks and physical verification on RF Integrated Circuits (RFIC ...
Senior Layout Extraction Engineer
$120K - $160K/yr
The Layout (FIRE) Extraction Engineer is an organized and highly motivated team player with strong ... mask fabrication and design rules (DRC) o Software/Tool Proficiency · Experience with OPC/Mask ...
Senior Layout Extraction Engineer
$120K - $160K/yr
The Layout (FIRE) Extraction Engineer is an organized and highly motivated team player with strong ... mask fabrication and design rules (DRC) o Software/Tool Proficiency · Experience with OPC/Mask ...
As a Layout Engineer you will be responsible for creating layouts to the specifications of the engineering team, and to perform design checks and physical verification on RF Integrated Circuits (RFIC ...
As a Layout Engineer you will be responsible for creating layouts to the specifications of the engineering team, and to perform design checks and physical verification on RF Integrated Circuits (RFIC ...
Entry Level Mask Layout Engineer information
See salary details
$40.5K - $49.8K
5% of jobs
$49.8K - $59K
10% of jobs
$64.9K is the 25th percentile. Wages below this are outliers.
$59K - $68.3K
16% of jobs
$68.3K - $77.6K
18% of jobs
The median wage is $78.4K / yr.
$77.6K - $86.9K
12% of jobs
$86.9K - $96.1K
11% of jobs
$99.7K is the 75th percentile. Wages above this are outliers.
$96.1K - $105.4K
10% of jobs
$105.4K - $114.7K
7% of jobs
$114.7K - $124K
5% of jobs
$124K - $133.2K
3% of jobs
$133.2K - $142.5K
3% of jobs
$40.5K
$86.4K
$142.5K
How much do entry level mask layout engineer jobs pay per year?
Texas Instruments rating
8.1
Based on 86 frontline employees who took The Breakroom Quiz
49th of 156 rated electronics manufacturers
Job description
Change the world. Love your job.
Texas Instruments is in an exciting era of growth and innovation, and our Advanced Technology Development (ATD) organization is at the center of it - developing the 28nm process technologies that will define TI's next generation of analog and embedded processing capabilities. As part of ATD, you won't just support production - you'll create the technology that makes it possible. Our engineers are working at the leading edge of computational lithography, Resolution Enhancement Techniques, and advanced process integration, solving the fundamental patterning and process challenges that determine whether a 28nm technology can be manufactured at scale and at yield. The work done in ATD directly enables fabs that will manufacture tens of millions of analog and embedded processing chips every day - supporting customer demand for decades to come. We're committed to responsible, sustainable semiconductor manufacturing and to building a diverse, technically excellent team that drives meaningful impact across the industry. In this role, you'll work at the intersection of fundamental research and high-volume manufacturing, turning process innovations into production-ready technologies that power electronics everywhere.
As a Resolution Enhancement Techniques (RET) Layout Engineer, you will architect new TI products and make our customers' visions a reality. You will define, design, model, implement, and document analog, digital, and RF integrated circuits (ICs).
Responsibilities will include, but are not limited to:
- Create layouts for setup, evaluation, and monitor of lithography/etch wafer processes.
- Work with fabrication process engineering and integration teams to determine specifications.
- Use design rules and/or existing layouts to create/modify test features.
- Maintain a list of measurement coordinate locations.
- Support and interaction for all fabs and technologies required.
- Create layouts for OPC development/monitor.
- Work with other RET engineers on layout and floor plan of test reticles for OPC model calibration and recipe development.
- Work with RET engineers to layout scribe modules for OPC model calibration/testing.
- Create layouts for reticle measurement and disposition.
- Work with other RET engineers and the PDK team to define specifications.
- Maintain a list of measurement coordinate locations.
- Work with RET, scribe, and design teams to create rules for layout placement.
- Develop and implement automation for producing layouts.
- Engineer your future. We empower our employees to truly own their career and development. Come collaborate with some of the smartest people in the world to shape the future of electronics.
- We're different by design. Diverse backgrounds and perspectives are what push innovation forward and what make TI stronger. We value each and every voice, and look forward to hearing yours. Meet the people of TI
- Benefits that benefit you. We offer competitive pay and benefits designed to help you and your family live your best life. Your well-being is important to us. Please find our country-specific benefits here
Minimum qualifications:
- Bachelors in Electrical Engineering, Physics, Computer Science, Chemistry or related degree
- Proficiency with EDA layout tools (Cadence suite, Synopsys, etc.) and scripting (e.g., Python, SKILL, Perl)
- 5+ years of experience in Layout/Mask design.
Preferred qualifications:
- Hands-on experience in design or PDK development with direct experience at a semiconductor company
- Excellent problem-solving, analytical, and communication skills for cross-team collaboration
- Experience working with PG flows
- Strong lithography knowledge
- OPC experience
What Texas Instruments employees say
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About Texas Instruments
Sourced by ZipRecruiter
As a global semiconductor company, we design, manufacture, test and sell analog and embedded processing chips to nearly 100,000 customers. Our products enable electronics everywhere and in things you experience every day - from health care, smart homes and connected cars to drones, smart phones and more. Our passion to create a better and more sustainable world by making electronics more affordable through semiconductors drives us to make our technology smaller, more efficient, more reliable and more affordable.
Industry
Semiconductor and electronic component manufacturing
Company size
10,000+ Employees
Headquarters location
Dallas, TX, US
Year founded
1930