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Mask Layout Engineer Jobs in California (NOW HIRING)

Qualcomm

Mask Layout Designer

San Diego, CA · On-site

Engineering Services Group, Engineering Services Group > Mask Layout Design General Summary: Qualcomm is a company of inventors that unlocked 5G, ushering in an age of rapid acceleration in ...

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Mask Layout Engineer information

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$44.4K

$119.3K

$183.1K

How much do mask layout engineer jobs pay per year?

As of Jul 14, 2026, the average yearly pay for mask layout engineer in California is $119,266.00, according to ZipRecruiter salary data. Most workers in this role earn between $88,800.00 and $142,100.00 per year, depending on experience, location, and employer.

What are the key skills and qualifications needed to thrive in the Mask Layout Engineer position, and why are they important?

A Mask Layout Engineer needs a solid background in semiconductor physics, microelectronics, and integrated circuit (IC) design, often supported by a relevant engineering degree. Proficiency with Electronic Design Automation (EDA) tools such as Cadence Virtuoso, Mentor Graphics, or Synopsys is typically required, and familiarity with industry standards like DRC/LVS checking is valuable. Strong attention to detail, problem-solving skills, and clear communication are important soft skills for collaborating with design and verification teams. These competencies are essential to ensure accurate, reliable IC layouts that meet stringent design and manufacturing specifications.

What is a Mask Layout Engineer job?

A Mask Layout Engineer is responsible for designing the physical layout of integrated circuits (ICs) based on schematic designs. They ensure that the layout meets design specifications, electrical performance criteria, and manufacturability constraints. This involves working with design rules, placement, routing, and verification tools to optimize performance and minimize errors. Mask Layout Engineers collaborate closely with circuit design teams, process engineers, and foundry teams to ensure that the final design can be successfully fabricated. Their work is critical in semiconductor manufacturing, impacting chip performance, size, and power efficiency.

What does a typical day look like for a Mask Layout Engineer?

A typical day for a Mask Layout Engineer involves translating circuit schematics into precise physical layouts using specialized software, running design rule checks (DRC) and layout versus schematic (LVS) verifications, and collaborating closely with circuit designers to resolve any issues or challenges. You’ll spend a significant portion of your time ensuring that layouts meet manufacturing process constraints and optimizing for performance and manufacturability. Mask Layout Engineers often work as part of a larger IC design team, interacting regularly with other engineers, project managers, and sometimes foundry partners. This role offers opportunities to deepen your technical skills and advance towards senior layout, design, or project leadership positions over time.

What are the most commonly searched types of Mask Layout Engineer jobs in California? The most popular types of Mask Layout Engineer jobs in California are:
What are popular job titles related to Mask Layout Engineer jobs in California? For Mask Layout Engineer jobs in California, the most frequently searched job titles are:
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What cities in California are hiring for Mask Layout Engineer jobs? Cities in California with the most Mask Layout Engineer job openings:
Mask Layout Engineer jobs near you
Infographic showing various Mask Layout Engineer job openings in California as of July 2026, with employment types broken down into 75% Full Time, and 25% Contract. Highlights an 75% In-person, and 25% Remote job distribution, with an average salary of $119,266 per year, or $57.3 per hour.

Sr.SRAM Mask Layout Engineer

TESSOLVE SEMICONDUCTOR PRIVATE LIMITED

Santa Clara, CA • On-site

Other

This job post has expired today. Applications are no longer accepted.

Job description

HI,

One of our valued customer is looking for Sr.SRAM Mask Layout Engineer at Santa clara,CA

Here is the JD for your reference :

Sr. SRAM Layout Design Engineer
Santa Clara,CA

Longterm Contract 

What you will be doing:
•    Manage the complete custom layout process for SRAM bitcell arrays, memory periphery, test structures, and memory macros in advanced CMOS technologies.
•    Develop and improve floorplans for SRAM and memory blocks, covering array layout, periphery positioning, power grid design, routing channels, and macro assembly.
•    Carry out, debug, and complete DRC, LVS, ERC, antenna, and associated physical verification checks with tools such as Calibre, ICV, or similar workflows.
•    Support EM/IR review, power integrity, density/fill, DFM, dummy insertion, layout-dependent effects, and other requirements for tapeout.
•    Collaborate with circuit designers to convert schematics into layouts, ensuring matching, symmetry, shielding, parasitic targets, and reliability constraints are maintained.
•    Collaborate with PnR and integration teams to resolve top-level DRC/LVS, pin access, boundary, routing, power-grid, and macro-integration issues.
•    Implement and advance layout methodology, checklists, reusable practices, and quality standards for consistent memory IP delivery.
•    Collaborate with foundry, CAD, and methodology teams on rule interpretation, deck behavior, waivers, and advanced-node process constraints.
•    Review layouts, mentor junior engineers, and help raise layout quality and execution rigor across the team.
 
What we need to see:
•    Have a BSEE or equivalent experience
•    10+ years of custom IC layout experience, including 5+ years in SRAM, memory compiler, or full-custom memory IP layout.
•    Hands-on participation in advanced CMOS technology initiatives, preferably concentrating on FinFET or GAA nodes at 5nm, 3nm, or smaller dimensions.
•    Solid grasp of SRAM and memory layout principles.
•    Extensive experience in Cadence Virtuoso applied to custom layout creation and assessment.
•    Extensive experience in DRC/LVS debugging using Calibre, ICV, or similar physical verification tools.
•    Experience with floorplanning, block-level routing, macro assembly, pin planning, boundary/interface management, and top-level physical verification.
•    Direct familiarity with advanced-node layout limitations and layout-dependent phenomena, including LOD, density/fill, matching, symmetry, shielding, electromigration, IR drop, and DFM or similar expertise.
•    Ability to work effectively with circuit build, physical build, integration, CAD, and foundry teams.
•    Clear communication, strong ownership, good judgment, and the ability to mentor other engineers.
•    Knowledge of layout automation or AI tools is a definite plus.
Please share resume:

About us:

Tessolve Semiconductors, a venture of Hero Electronix, is a Design and Test Engineering Service Company providing End to End Solutions from Product Engineering, Software, Hardware, Wireless, Automotive and Embedded Solutions. Tessolve offers a unique combination of pre-silicon and post-silicon expertise to provide an efficient turnkey solution for silicon bring-up, spec to the product. With 2500+ employees worldwide, Tessolve provides a one-stop-shop solution with full-fledged hardware and software capabilities, including its advanced silicon and system testing labs. Tessolve offers a Turnkey ASIC Solution, from design to packaged parts. We have a global presence with office locations in the United States, India, Singapore, Malaysia, Germany, United Kingdom, China, UK, Japan, Thailand, Philippines, and Test Labs in India, Singapore, Malaysia, Austin, San Jose. Tessolve offers a highly competitive compensation and benefits along with an electric work environment to scale one’s intellect, skills and growth.

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