Santa Clara, CA · Hybrid
$122K - $164K/yr
Are you a Mask Layout Design Engineer who is seeking am amazing opportunity? We are looking for a Senior Mask Layout Design Engineer - someone who is excited to join a growing group of diverse ...
Santa Clara, CA · Hybrid
$122K - $164K/yr
Are you a Mask Layout Design Engineer who is seeking am amazing opportunity? We are looking for a Senior Mask Layout Design Engineer - someone who is excited to join a growing group of diverse ...
As an Analog IC Layout Engineer, your responsibilities will include: * Crafting state-of-the-art ... Physical verification of custom IC mask layouts (LVS, DRC, ERC) Required Qualifications: * 2+ years ...
As an Analog IC Layout Engineer, your responsibilities will include: * Crafting state-of-the-art ... Physical verification of custom IC mask layouts (LVS, DRC, ERC) Required Qualifications: * 2+ years ...
$137K - $250K/yr
Capability to lead other layout engineers for top-level integration. Scripting skills in PERL or SKILL are a plus. Extensive knowledge of CADENCE layout tools. Minimum Qualifications BS and 3+ years ...
$137K - $250K/yr
Capability to lead other layout engineers for top-level integration. Scripting skills in PERL or SKILL are a plus. Extensive knowledge of CADENCE layout tools. Minimum Qualifications BS and 3+ years ...
$137K - $250K/yr
Capability to lead other layout engineers for top-level integration. Scripting skills in PERL or SKILL are a plus. Extensive knowledge of CADENCE layout tools. Minimum Qualifications BS and 3+ years ...
$137K - $250K/yr
Capability to lead other layout engineers for top-level integration. Scripting skills in PERL or SKILL are a plus. Extensive knowledge of CADENCE layout tools. Minimum Qualifications BS and 3+ years ...
$166K - $296K/yr
Top-level layout integration and verification, schedule management.","responsibilities":"As a RF layout engineer, you will be responsible for: Detailed transistor-level layout of RF and analog ...
$166K - $296K/yr
Top-level layout integration and verification, schedule management.","responsibilities":"As a RF layout engineer, you will be responsible for: Detailed transistor-level layout of RF and analog ...
$43.07 - $76.64/hr
Capability to lead other layout engineers for top-level integration. Minimum Qualifications 8+ year minimum related experience required Good understanding of RC delay, electromigration, and coupling.
$43.07 - $76.64/hr
Capability to lead other layout engineers for top-level integration. Minimum Qualifications 8+ year minimum related experience required Good understanding of RC delay, electromigration, and coupling.
$43.07 - $76.64/hr
Capability to lead other layout engineers for top-level integration. Minimum Qualifications 8+ year minimum related experience required Good understanding of RC delay, electromigration, and coupling.
$43.07 - $76.64/hr
Capability to lead other layout engineers for top-level integration. Minimum Qualifications 8+ year minimum related experience required Good understanding of RC delay, electromigration, and coupling.
$166K - $296K/yr
Top-level layout integration and verification, schedule management.","responsibilities":"As a RF layout engineer, you will be responsible for: Detailed transistor-level layout of RF and analog ...
$166K - $296K/yr
Top-level layout integration and verification, schedule management.","responsibilities":"As a RF layout engineer, you will be responsible for: Detailed transistor-level layout of RF and analog ...
Irvine, CA · On-site
Capability to lead other layout engineers for top-level integration. Scripting skills in PERL or SKILL are a plus.
Irvine, CA · On-site
Capability to lead other layout engineers for top-level integration. Scripting skills in PERL or SKILL are a plus.
$137K - $250K/yr
Capability to lead other layout engineers for top-level integration. Scripting skills in PERL or SKILL are a plus. Extensive knowledge of CADENCE layout tools. Minimum Qualifications BS and 3+ years ...
$137K - $250K/yr
Capability to lead other layout engineers for top-level integration. Scripting skills in PERL or SKILL are a plus. Extensive knowledge of CADENCE layout tools. Minimum Qualifications BS and 3+ years ...
$43.07 - $76.64/hr
Capability to lead other layout engineers for top-level integration. Minimum Qualifications 8+ year minimum related experience required Good understanding of RC delay, electromigration, and coupling.
$43.07 - $76.64/hr
Capability to lead other layout engineers for top-level integration. Minimum Qualifications 8+ year minimum related experience required Good understanding of RC delay, electromigration, and coupling.
$166K - $296K/yr
Top-level layout integration and verification, schedule management.","responsibilities":"As a RF layout engineer, you will be responsible for: Detailed transistor-level layout of RF and analog ...
$166K - $296K/yr
Top-level layout integration and verification, schedule management.","responsibilities":"As a RF layout engineer, you will be responsible for: Detailed transistor-level layout of RF and analog ...
Temecula, CA · On-site
$125K - $185K/yr
All tasks related to mask design and layout of photonic integrated circuits * Creating mask designs in conjunction with optical designers and process engineers. * Creating design rules and ...
Quick apply
Temecula, CA · On-site
$125K - $185K/yr
All tasks related to mask design and layout of photonic integrated circuits * Creating mask designs in conjunction with optical designers and process engineers. * Creating design rules and ...
Irvine, CA · On-site
Capability to lead other layout engineers for top-level integration.
Irvine, CA · On-site
Capability to lead other layout engineers for top-level integration.
Irvine, CA · On-site
Capability to lead other layout engineers for top-level integration. Scripting skills in PERL or SKILL are a plus. Extensive knowledge of CADENCE layout tools.
Irvine, CA · On-site
Capability to lead other layout engineers for top-level integration. Scripting skills in PERL or SKILL are a plus. Extensive knowledge of CADENCE layout tools.
$125K - $185K/yr
All tasks related to mask design and layout of photonic integrated circuits * Creating mask designs in conjunction with optical designers and process engineers. * Creating design rules and ...
$125K - $185K/yr
All tasks related to mask design and layout of photonic integrated circuits * Creating mask designs in conjunction with optical designers and process engineers. * Creating design rules and ...
Fremont, CA · On-site
$83K - $139K/yr
As an Analog IC Layout Engineer, your responsibilities will include: * Crafting state-of-the-art ... Physical verification of custom IC mask layouts (LVS, DRC, ERC) Required Qualifications: * 2+ years ...
Fremont, CA · On-site
$83K - $139K/yr
As an Analog IC Layout Engineer, your responsibilities will include: * Crafting state-of-the-art ... Physical verification of custom IC mask layouts (LVS, DRC, ERC) Required Qualifications: * 2+ years ...
We are looking for a Senior Mask Layout Design Engineer, someone who is excited to join a growing and dynamic group of diverse individuals responsible for handling meaningful high-speed mixed-signal ...
We are looking for a Senior Mask Layout Design Engineer, someone who is excited to join a growing and dynamic group of diverse individuals responsible for handling meaningful high-speed mixed-signal ...
We are looking for a Senior Mask Layout Design Engineer, someone who is excited to join a growing and dynamic group of diverse individuals responsible for handling meaningful high-speed mixed-signal ...
We are looking for a Senior Mask Layout Design Engineer, someone who is excited to join a growing and dynamic group of diverse individuals responsible for handling meaningful high-speed mixed-signal ...
We are looking for a Senior Mask Layout Design Engineer, someone who is excited to join a growing and dynamic group of diverse individuals responsible for handling meaningful high-speed mixed-signal ...
We are looking for a Senior Mask Layout Design Engineer, someone who is excited to join a growing and dynamic group of diverse individuals responsible for handling meaningful high-speed mixed-signal ...
$44.4K - $57K
4% of jobs
$57K - $69.6K
2% of jobs
$69.6K - $82.2K
12% of jobs
$92.5K is the 25th percentile. Wages below this are outliers.
$82.2K - $94.8K
9% of jobs
$94.8K - $107.4K
11% of jobs
The median wage is $119.1K / yr.
$107.4K - $120K
14% of jobs
$120K - $132.6K
22% of jobs
$135K is the 75th percentile. Wages above this are outliers.
$132.6K - $145.3K
9% of jobs
$145.3K - $157.9K
9% of jobs
$157.9K - $170.5K
3% of jobs
$170.5K - $183.1K
6% of jobs
$44.4K
$119.3K
$183.1K
A Mask Layout Engineer needs a solid background in semiconductor physics, microelectronics, and integrated circuit (IC) design, often supported by a relevant engineering degree. Proficiency with Electronic Design Automation (EDA) tools such as Cadence Virtuoso, Mentor Graphics, or Synopsys is typically required, and familiarity with industry standards like DRC/LVS checking is valuable. Strong attention to detail, problem-solving skills, and clear communication are important soft skills for collaborating with design and verification teams. These competencies are essential to ensure accurate, reliable IC layouts that meet stringent design and manufacturing specifications.
A Mask Layout Engineer is responsible for designing the physical layout of integrated circuits (ICs) based on schematic designs. They ensure that the layout meets design specifications, electrical performance criteria, and manufacturability constraints. This involves working with design rules, placement, routing, and verification tools to optimize performance and minimize errors. Mask Layout Engineers collaborate closely with circuit design teams, process engineers, and foundry teams to ensure that the final design can be successfully fabricated. Their work is critical in semiconductor manufacturing, impacting chip performance, size, and power efficiency.
A typical day for a Mask Layout Engineer involves translating circuit schematics into precise physical layouts using specialized software, running design rule checks (DRC) and layout versus schematic (LVS) verifications, and collaborating closely with circuit designers to resolve any issues or challenges. You’ll spend a significant portion of your time ensuring that layouts meet manufacturing process constraints and optimizing for performance and manufacturability. Mask Layout Engineers often work as part of a larger IC design team, interacting regularly with other engineers, project managers, and sometimes foundry partners. This role offers opportunities to deepen your technical skills and advance towards senior layout, design, or project leadership positions over time.
$122K - $164K/yr
Full-time
Re-posted 8 days ago
9.3
Based on 5 frontline employees who took The Breakroom Quiz
15th of 209 rated software companies
Are you a Mask Layout Design Engineer who is seeking am amazing opportunity? We are looking for a Senior Mask Layout Design Engineer - someone who is excited to join a growing group of diverse individuals responsible for handling complex mixed-signal circuit designs! NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in 1999 fueled the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. More recently, GPU deep learning ignited modern AI - the next era of computing. NVIDIA is a "learning machine" that constantly evolves by adapting to new opportunities that are hard to solve, that only we can pursue, and that matter to the world. This is our life's work, to amplify human creativity and intelligence. Join our dynamic team today!
What you'll be doing:
The role entails working collaboratively and multi-functionally with a multi-disciplinary team of Photonics, CMOS, Electronics, and Systems engineers
Perform physical layout for mixed-signal functions like PLL's, high speed I/O circuits, general I/O's, ESD structures designs in innovative sub-micron CMOS technologies using Cadence tools
You'll work with ASIC and mixed-signal engineers to customize designs for integration in VLSI products.
Job duties will include floor planning, custom layout and verifying against design rules and schematics.
Fill, post-processing, DRC mitigation, and foundry interactions
What we need to see:
BS in Electrical Engineering (or equivalent experience)
At least 6+ years of hands-on layout design experience
Deep understanding of analog circuit layout concepts in submicron CMOS technologies. Validated experience with Cadence custom circuit design tools - particularly virtuoso
Experience running and debugging DRC and LVS with verification tools such as Dracula, Hercules, Calibre, Primeyield
Ability to work optimally in a team, good interpersonal skills and positive energy.
Proficiency in scripting languages like perl, python, skill etc. Knowledge of DRC and LVS checking flows, ability to customize DRC and LVS
NVIDIA is widely considered to be one of the technology world's most desirable employers. We have some of the most forward-thinking and talented people in the world working for us. If you're creative and autonomous, we want to hear from you.
#LI-Hybrid
You will also be eligible for equity and benefits.
This posting is for an existing vacancy.
NVIDIA uses AI tools in its recruiting processes.
NVIDIA is committed to fostering an inclusive work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law.
Sourced by ZipRecruiter
NVIDIA has been transforming computer graphics, PC gaming, and accelerated computing for more than 25 years. It's a unique legacy of innovation that's fueled by great technology--and amazing people. Today, we're tapping into the unlimited potential of AI to define the next era of computing. An era in which our GPU acts as the brains of computers, robots, and self-driving cars that can understand the world. Doing what's never been done before takes vision, innovation, and the world's best talent.
Computer and electronic product manufacturing
10,000+ Employees
Santa Clara, CA, US
1993
