Apple's Silicon Security team is looking for a driven ASIC Design Engineer to build the secure ... Familiarity with low-power design techniques and UPF (Unified Power Format). Solid understanding of ...
Apple's Silicon Security team is looking for a driven ASIC Design Engineer to build the secure ... Familiarity with low-power design techniques and UPF (Unified Power Format). Solid understanding of ...
Apple's Silicon Security team is looking for a driven ASIC Design Engineer to build the secure ... Familiarity with low-power design techniques and UPF (Unified Power Format). Solid understanding of ...
Apple's Silicon Security team is looking for a driven ASIC Design Engineer to build the secure ... Familiarity with low-power design techniques and UPF (Unified Power Format). Solid understanding of ...
ASIC Design and Integration Engineer
Beaverton, OR · On-site
$150K - $277K/yr
Apple's Silicon Engineering team is looking for a highly skilled and motivated ASIC Design Engineer ... Knowledge of low-power design techniques and power optimization strategies. Minimum Qualifications ...
ASIC Design and Integration Engineer
Beaverton, OR · On-site
$150K - $277K/yr
Apple's Silicon Engineering team is looking for a highly skilled and motivated ASIC Design Engineer ... Knowledge of low-power design techniques and power optimization strategies. Minimum Qualifications ...
ASIC Design and Integration Engineer
Beaverton, OR · On-site
$184K - $324K/yr
Apple's Silicon Engineering team is looking for a highly skilled and motivated ASIC Design Engineer ... Knowledge of low-power design techniques and power optimization strategies. Minimum Qualifications ...
ASIC Design and Integration Engineer
Beaverton, OR · On-site
$184K - $324K/yr
Apple's Silicon Engineering team is looking for a highly skilled and motivated ASIC Design Engineer ... Knowledge of low-power design techniques and power optimization strategies. Minimum Qualifications ...
ASIC Design and Integration Engineer
$184K - $324K/yr
Apple's Silicon Engineering team is looking for a highly skilled and motivated ASIC Design Engineer ... Knowledge of low-power design techniques and power optimization strategies. Minimum Qualifications ...
ASIC Design and Integration Engineer
$184K - $324K/yr
Apple's Silicon Engineering team is looking for a highly skilled and motivated ASIC Design Engineer ... Knowledge of low-power design techniques and power optimization strategies. Minimum Qualifications ...
ASIC Design Engineer (Hardware Security)
San Diego, CA · On-site
$140K - $229K/yr
Experience with high-speed, low-area, and low-power architecture. * Experience in hardware security ... Bachelor's degree in Science, Engineering, or related field and 6+ years of ASIC design ...
ASIC Design Engineer (Hardware Security)
San Diego, CA · On-site
$140K - $229K/yr
Experience with high-speed, low-area, and low-power architecture. * Experience in hardware security ... Bachelor's degree in Science, Engineering, or related field and 6+ years of ASIC design ...
Description As an ASIC Design Engineer in the Pixel IP design team, you will work closely with architecture, design, and verification teams to design high performance and low power pixel processing ...
Description As an ASIC Design Engineer in the Pixel IP design team, you will work closely with architecture, design, and verification teams to design high performance and low power pixel processing ...
ASIC Physical Design Engineer, Principal
$200K - $220K/yr
... specialized engineers with over 25 years of ASIC/FPGA experience and more than 300 patents ... Knowledge of low power design flows such as power gating, multi-Vt, Voltage scaling techniques*
ASIC Physical Design Engineer, Principal
$200K - $220K/yr
... specialized engineers with over 25 years of ASIC/FPGA experience and more than 300 patents ... Knowledge of low power design flows such as power gating, multi-Vt, Voltage scaling techniques*
... low-power solutions that exceed comparable commercial alternatives. We are seeking an experienced senior physical design ASIC design engineer, to help us advance the state-of-the-art in miniature ...
... low-power solutions that exceed comparable commercial alternatives. We are seeking an experienced senior physical design ASIC design engineer, to help us advance the state-of-the-art in miniature ...
Digital ASIC Design Engineer for Mixed-Signal IPs
San Diego, CA · On-site
$115K - $173K/yr
Strong background in low-power digital design techniques * 2+ years of hands‑on experience in RTL ... Bachelor's degree in Science, Engineering, or related field and 2+ years of ASIC design ...
Digital ASIC Design Engineer for Mixed-Signal IPs
San Diego, CA · On-site
$115K - $173K/yr
Strong background in low-power digital design techniques * 2+ years of hands‑on experience in RTL ... Bachelor's degree in Science, Engineering, or related field and 2+ years of ASIC design ...
Principal ASIC Design Engineer (Starshield)
$200K - $285K/yr
Experience with high speed and low power design techniques. * Scripting skills (Python, TCL etc ... Principal ASIC Design Engineer: $200,000.00 - $285,000.00/per year Your actual level and base ...
Principal ASIC Design Engineer (Starshield)
$200K - $285K/yr
Experience with high speed and low power design techniques. * Scripting skills (Python, TCL etc ... Principal ASIC Design Engineer: $200,000.00 - $285,000.00/per year Your actual level and base ...
As a member of the NVLink ASIC Design team, you will work with a worldwide team of architects and engineers dedicated to building high-speed chip-to-chip communication and high-performance, low-power ...
As a member of the NVLink ASIC Design team, you will work with a worldwide team of architects and engineers dedicated to building high-speed chip-to-chip communication and high-performance, low-power ...
Why This Role Matters As a Sr. ASIC Design Engineer on our Blink/Ring ASIC Team, you'll work on ... We work backwards from real customer needs to create super-low power, energy-efficient designs ...
Why This Role Matters As a Sr. ASIC Design Engineer on our Blink/Ring ASIC Team, you'll work on ... We work backwards from real customer needs to create super-low power, energy-efficient designs ...
As a member of the NVLink ASIC Design team, you will work with a worldwide team of architects and engineers dedicated to building high-speed chip-to-chip communication and high-performance, low-power ...
As a member of the NVLink ASIC Design team, you will work with a worldwide team of architects and engineers dedicated to building high-speed chip-to-chip communication and high-performance, low-power ...
ASIC Design Engineer - DSP / Analog / SerDes
Irvine, CA · On-site
$150K - $250K/yr
ASIC Design Engineer - DSP / Analog / SerDes Celero Communications is an exciting and fast-growing ... Knowledge of low-power design techniques and PPA optimization. Strong analytical and problem ...
ASIC Design Engineer - DSP / Analog / SerDes
Irvine, CA · On-site
$150K - $250K/yr
ASIC Design Engineer - DSP / Analog / SerDes Celero Communications is an exciting and fast-growing ... Knowledge of low-power design techniques and PPA optimization. Strong analytical and problem ...
... Design engineers with solid ASIC design experience in San Diego, CA. This is a high-level, high ... Experience with High-speed, Low Area, and Low Power architecture * Experience in hardware security ...
... Design engineers with solid ASIC design experience in San Diego, CA. This is a high-level, high ... Experience with High-speed, Low Area, and Low Power architecture * Experience in hardware security ...
As a member of the NVLink ASIC Design team, you will work with a worldwide team of architects and engineers dedicated to building high-speed chip-to-chip communication and high-performance, low-power ...
As a member of the NVLink ASIC Design team, you will work with a worldwide team of architects and engineers dedicated to building high-speed chip-to-chip communication and high-performance, low-power ...
ASIC Design Engineer - DSP / Analog / SerDes
San Jose, CA · On-site
$150K - $250K/yr
ASIC Design Engineer - DSP / Analog / SerDes Celero Communications is an exciting and fast-growing ... Knowledge of low-power design techniques and PPA optimization. Strong analytical and problem ...
ASIC Design Engineer - DSP / Analog / SerDes
San Jose, CA · On-site
$150K - $250K/yr
ASIC Design Engineer - DSP / Analog / SerDes Celero Communications is an exciting and fast-growing ... Knowledge of low-power design techniques and PPA optimization. Strong analytical and problem ...
Description As an ASIC Design Engineer in the Pixel IP design team, you be responsible for complex ... Prefer experience in low-power design, tools, and methodologies including UPF power intent ...
Description As an ASIC Design Engineer in the Pixel IP design team, you be responsible for complex ... Prefer experience in low-power design, tools, and methodologies including UPF power intent ...
Why This Role Matters As a Sr. ASIC Design Engineer on our Blink/Ring ASIC Team, you'll work on ... We work backwards from real customer needs to create super-low power, energy-efficient designs ...
Why This Role Matters As a Sr. ASIC Design Engineer on our Blink/Ring ASIC Team, you'll work on ... We work backwards from real customer needs to create super-low power, energy-efficient designs ...
Low Power Asic Design Engineer information
See salary details
$94K - $103.8K
16% of jobs
$103.8K - $113.6K
3% of jobs
$113.6K - $123.5K
4% of jobs
$126.3K is the 25th percentile. Wages below this are outliers.
$123.5K - $133.3K
6% of jobs
The median wage is $139.4K / yr.
$133.3K - $143.1K
33% of jobs
$143.1K - $152.9K
3% of jobs
$152.9K - $162.7K
2% of jobs
$169.2K is the 75th percentile. Wages above this are outliers.
$162.7K - $172.5K
12% of jobs
$172.5K - $182.4K
5% of jobs
$182.4K - $192.2K
4% of jobs
$192.2K - $202K
12% of jobs
$94K
$150.2K
$202K
How much do low power asic design engineer jobs pay per year?
What does a low power ASIC design engineer do?
What are the key skills and qualifications needed to thrive as a low power ASIC design engineer?
What are some common challenges faced by low power ASIC design engineers when optimizing circuits for minimal energy consumption?
What is the difference between Low Power Asic Design Engineer vs Digital ASIC Design Engineer?
| Aspect | Low Power ASIC Design Engineer | Digital ASIC Design Engineer |
|---|---|---|
| Focus | Designing ASICs optimized for low power consumption | Designing digital ASICs with a focus on performance and functionality |
| Skills | Low power techniques, power analysis, low power verification | Digital logic design, RTL coding, verification |
| Work Environment | Semiconductor companies, chip design firms | Semiconductor companies, integrated circuit design firms |
| Certifications | ASIC design, low power design courses | ASIC design, digital design certifications |
While both roles involve ASIC design, the Low Power ASIC Design Engineer specializes in reducing power consumption, whereas the Digital ASIC Design Engineer focuses on digital logic and performance. The roles often overlap, but the primary distinction lies in the emphasis on power optimization versus digital functionality.
What are popular job titles related to Low Power Asic Design Engineer jobs?
For Low Power Asic Design Engineer jobs, the most frequently searched job titles are:

ASIC Design and Integration Engineer - Silicon Security
Cupertino, CA • On-site
Full-time
Re-posted 5 days ago
Apple rating
8.1
Based on 684 frontline employees who took The Breakroom Quiz
6th of 30 rated technology retailers
Job description
Description
As an ASIC Design Engineer on the Silicon Security team, you will be responsible for the micro-architecture, RTL design and integration of secure subsystems. Your responsibilities will include:
• Architecting and designing state-of-the-art security features, working closely with Platform Architecture, Design Verification to deliver high performance, area and power efficient RTL Blocks on time
• Integrating security IPs into secure subsystem and ensuring timing, performance and security requirements are met.
• Resolving integration issues across multiple IP blocks and coordinating with IP owners on interface and functionality concerns
• Driving front-end quality flows from RTL to netlist, including hands-on work with Lint, CDC/RDC analysis, UPF development, timing, and Synthesis.
• Leveraging AI-assisted tools to enhance design quality and productivity.
Minimum Qualifications
Bachelors in Electrical Engineering, Computer Engineering or a relevant field and 10 years of industry experience
10 years of RTL design experience using Verilog or SystemVerilog.
Preferred Qualifications
Experience with CDC (Clock Domain Crossing) and RDC (Reset Domain Crossing) analysis and verification.
Familiarity with low-power design techniques and UPF (Unified Power Format).
Solid understanding of digital design fundamentals including synthesis, timing closure, and design for testability.
Background in cryptography and cryptographic algorithm implementation.
Experience with hardware security concepts including key management, physical attack and countermeasures.
Experience with clock and reset architecture at the subsystem level
Strong knowledge of AMBA bus protocols (AXI, AHB, APB).
Experience with hardware security concepts including key management, physical attack and countermeasures
About Apple
Sourced by ZipRecruiter
Imagine what you could do here! At Apple, new ideas have a way of becoming extraordinary products, services, and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could accomplish. Dynamic, intelligent people and inspiring, innovative technologies are the norm here. The people who work here have reinvented entire industries with all Apple Hardware products. The same real passion for innovation that goes into our products also applies to our practices strengthening our dedication to leave the world better than we found it.
Industry
Computer and electronic product manufacturing
Company size
10,000+ Employees
Headquarters location
Cupertino, CA, US
Year founded
1976