ASIC Design Engineer( Remote) MUST HAVE: AEROSPACE , DEEP UNDERSTANDING ASIC, DO254, DIGITAL ... Design and develop high-performance, low-power, and highly reliable ASICs for aerospace systems ...
ASIC Design Engineer( Remote) MUST HAVE: AEROSPACE , DEEP UNDERSTANDING ASIC, DO254, DIGITAL ... Design and develop high-performance, low-power, and highly reliable ASICs for aerospace systems ...
ASIC Design And Integration Engineer Apple's Silicon Engineering team is looking for a highly ... Knowledge of low-power design techniques and power optimization strategies.
ASIC Design And Integration Engineer Apple's Silicon Engineering team is looking for a highly ... Knowledge of low-power design techniques and power optimization strategies.
Principal ASIC Design Engineer
Moundsview, MN · On-site
We have an integrated ASIC team enabling engineers to wear many hats from digital design ... Low power design methods and power analysis * Digital Signal Processing (DSP) * Developing for ...
Principal ASIC Design Engineer
Moundsview, MN · On-site
We have an integrated ASIC team enabling engineers to wear many hats from digital design ... Low power design methods and power analysis * Digital Signal Processing (DSP) * Developing for ...
Principal ASIC Design Engineer
Moundsview, MN · On-site
We have an integrated ASIC team enabling engineers to wear many hats from digital design ... Low power design methods and power analysis * Digital Signal Processing (DSP) * Developing for ...
Principal ASIC Design Engineer
Moundsview, MN · On-site
We have an integrated ASIC team enabling engineers to wear many hats from digital design ... Low power design methods and power analysis * Digital Signal Processing (DSP) * Developing for ...
Apple's Silicon Engineering team is looking for a highly skilled and motivated ASIC Design Engineer ... Knowledge of low-power design techniques and power optimization strategies.
Apple's Silicon Engineering team is looking for a highly skilled and motivated ASIC Design Engineer ... Knowledge of low-power design techniques and power optimization strategies.
Apple's Silicon Engineering team is looking for a highly skilled and motivated ASIC Design Engineer ... Knowledge of low-power design techniques and power optimization strategies. Minimum Qualifications ...
Apple's Silicon Engineering team is looking for a highly skilled and motivated ASIC Design Engineer ... Knowledge of low-power design techniques and power optimization strategies. Minimum Qualifications ...
Apple's Silicon Engineering team is looking for a highly skilled and motivated ASIC Design Engineer ... Knowledge of low-power design techniques and power optimization strategies. Minimum Qualifications ...
Apple's Silicon Engineering team is looking for a highly skilled and motivated ASIC Design Engineer ... Knowledge of low-power design techniques and power optimization strategies. Minimum Qualifications ...
Apple's Silicon Engineering team is looking for a highly skilled and motivated ASIC Design Engineer ... Knowledge of low-power design techniques and power optimization strategies.
Apple's Silicon Engineering team is looking for a highly skilled and motivated ASIC Design Engineer ... Knowledge of low-power design techniques and power optimization strategies.
ASIC RTL Design Engineer
Santa Clara, CA · On-site
ASIC RTL Design Engineer Responsible for microarchitecture and RTL design of high performance data ... Write high performance and low power Verilog RTL, synthesis and timing closure. Collaborate with ...
New
ASIC RTL Design Engineer
Santa Clara, CA · On-site
ASIC RTL Design Engineer Responsible for microarchitecture and RTL design of high performance data ... Write high performance and low power Verilog RTL, synthesis and timing closure. Collaborate with ...
New
ASIC Design Engineer Responsibilities: * Define and bring up FPGA platforms for pre-silicon ... Experience with validating and debugging low-power wireless systems * Understanding of common ...
Quick apply
ASIC Design Engineer Responsibilities: * Define and bring up FPGA platforms for pre-silicon ... Experience with validating and debugging low-power wireless systems * Understanding of common ...
Design Engineer (Low Power)
Santa Clara, CA · On-site
$176K - $264K/yr
... Low Power micro-architecture, Power Intent/Implementation, power estimates and power reduction ... The candidate will work hands-on and own their design through the full ASIC development process ...
Design Engineer (Low Power)
Santa Clara, CA · On-site
$176K - $264K/yr
... Low Power micro-architecture, Power Intent/Implementation, power estimates and power reduction ... The candidate will work hands-on and own their design through the full ASIC development process ...
ASIC Design Engineer - Staff
Irvine, CA · On-site
$150K - $250K/yr
Celero is seeking skilled and motivated ASIC Design Engineers to join our team and contribute to ... Knowledge of low-power design techniques. * Familiarity with verification methodologies (e.g., UVM ...
ASIC Design Engineer - Staff
Irvine, CA · On-site
$150K - $250K/yr
Celero is seeking skilled and motivated ASIC Design Engineers to join our team and contribute to ... Knowledge of low-power design techniques. * Familiarity with verification methodologies (e.g., UVM ...
ASIC Design Engineer - Staff
Irvine, CA · On-site
$150K - $250K/yr
Celero is seeking skilled and motivated ASIC Design Engineers to join our team and contribute to ... Knowledge of low-power design techniques. * Familiarity with verification methodologies (e.g., UVM ...
ASIC Design Engineer - Staff
Irvine, CA · On-site
$150K - $250K/yr
Celero is seeking skilled and motivated ASIC Design Engineers to join our team and contribute to ... Knowledge of low-power design techniques. * Familiarity with verification methodologies (e.g., UVM ...
Principal ASIC Design Engineer
Moundsview, MN · On-site
We have an integrated ASIC team enabling engineers to wear many hats from digital design ... Low power design methods and power analysis * Digital Signal Processing (DSP) * Developing for ...
Principal ASIC Design Engineer
Moundsview, MN · On-site
We have an integrated ASIC team enabling engineers to wear many hats from digital design ... Low power design methods and power analysis * Digital Signal Processing (DSP) * Developing for ...
Principal ASIC Design Engineer
Moundsview, MN · On-site
We have an integrated ASIC team enabling engineers to wear many hats from digital design ... Low power design methods and power analysis * Digital Signal Processing (DSP) * Developing for ...
Principal ASIC Design Engineer
Moundsview, MN · On-site
We have an integrated ASIC team enabling engineers to wear many hats from digital design ... Low power design methods and power analysis * Digital Signal Processing (DSP) * Developing for ...
Proficiency with UPF (Low power intent) * Proficiency in clock crossing techniques. * Knowledge of Static Timing Analysis and understanding of timing signoff fundamentals. What we are looking for:
Proficiency with UPF (Low power intent) * Proficiency in clock crossing techniques. * Knowledge of Static Timing Analysis and understanding of timing signoff fundamentals. What we are looking for:
ASIC Design Engineer (eInfochips)
Austin, TX · On-site +1
Proficiency with UPF (Low power intent) * Proficiency in clock crossing techniques. * Knowledge of Static Timing Analysis and understanding of timing signoff fundamentals. What we are looking for:
ASIC Design Engineer (eInfochips)
Austin, TX · On-site +1
Proficiency with UPF (Low power intent) * Proficiency in clock crossing techniques. * Knowledge of Static Timing Analysis and understanding of timing signoff fundamentals. What we are looking for:
ASIC Design Engineer (eInfochips)
Mountain View, CA · On-site +1
Proficiency with UPF (Low power intent) * Proficiency in clock crossing techniques. * Knowledge of Static Timing Analysis and understanding of timing signoff fundamentals. What we are looking for:
ASIC Design Engineer (eInfochips)
Mountain View, CA · On-site +1
Proficiency with UPF (Low power intent) * Proficiency in clock crossing techniques. * Knowledge of Static Timing Analysis and understanding of timing signoff fundamentals. What we are looking for:
Wireless Design Engineer
$171K - $302K/yr
As a Wireless Design Engineer, you will be responsible for RTL design of wireless MAC and its ... low power ASIC design for wireless MAC, including: Writing specifications and other documents ...
Wireless Design Engineer
$171K - $302K/yr
As a Wireless Design Engineer, you will be responsible for RTL design of wireless MAC and its ... low power ASIC design for wireless MAC, including: Writing specifications and other documents ...
Wireless Design Engineer
$171K - $302K/yr
As a Wireless Design Engineer, you will be responsible for RTL design of wireless MAC and its ... low power ASIC design for wireless MAC, including: Writing specifications and other documents ...
Wireless Design Engineer
$171K - $302K/yr
As a Wireless Design Engineer, you will be responsible for RTL design of wireless MAC and its ... low power ASIC design for wireless MAC, including: Writing specifications and other documents ...
Low Power Asic Design Engineer information
See salary details
$94K - $103.8K
16% of jobs
$103.8K - $113.6K
3% of jobs
$113.6K - $123.5K
4% of jobs
$126.3K is the 25th percentile. Wages below this are outliers.
$123.5K - $133.3K
6% of jobs
The median wage is $139.4K / yr.
$133.3K - $143.1K
33% of jobs
$143.1K - $152.9K
3% of jobs
$152.9K - $162.7K
2% of jobs
$169.2K is the 75th percentile. Wages above this are outliers.
$162.7K - $172.5K
12% of jobs
$172.5K - $182.4K
5% of jobs
$182.4K - $192.2K
4% of jobs
$192.2K - $202K
12% of jobs
$94K
$150.2K
$202K
How much do low power asic design engineer jobs pay per year?
What are some common challenges faced by Low Power ASIC Design Engineers when optimizing circuits for minimal energy consumption?
What are the key skills and qualifications needed to thrive as a Low Power ASIC Design Engineer, and why are they important?
What does a Low Power ASIC Design Engineer do?
What is the difference between Low Power Asic Design Engineer vs Digital ASIC Design Engineer?
| Aspect | Low Power ASIC Design Engineer | Digital ASIC Design Engineer |
|---|---|---|
| Focus | Designing ASICs optimized for low power consumption | Designing digital ASICs with a focus on performance and functionality |
| Skills | Low power techniques, power analysis, low power verification | Digital logic design, RTL coding, verification |
| Work Environment | Semiconductor companies, chip design firms | Semiconductor companies, integrated circuit design firms |
| Certifications | ASIC design, low power design courses | ASIC design, digital design certifications |
While both roles involve ASIC design, the Low Power ASIC Design Engineer specializes in reducing power consumption, whereas the Digital ASIC Design Engineer focuses on digital logic and performance. The roles often overlap, but the primary distinction lies in the emphasis on power optimization versus digital functionality.

Full-time
Posted 22 days ago
Job description
MUST HAVE: AEROSPACE , DEEP UNDERSTANDING ASIC, DO254, DIGITAL CIRCUITS
Position Overview:
We are looking for an experienced ASIC Design Engineer with a strong background in the design, verification, and implementation of Application-Specific Integrated Circuits (ASICs) for aerospace applications. The ideal candidate will have extensive experience working on high-reliability, high-performance digital circuits, and a deep understanding of ASIC design processes, in consideration of DO254.
- Key Responsibilities:
- ASIC Design and Development: Design and develop high-performance, low-power, and highly reliable ASICs for aerospace systems, ensuring compliance with stringent aerospace industry standards like DO254 .
- System-Level Design Integration: Work closely with system engineers to ensure seamless integration of ASICs into larger aerospace systems, including payloads, communications, and avionics systems.
- Verification and Testing: Conduct thorough verification and validation of ASIC designs, including functional verification, timing analysis, and design for testability (DFT). Perform failure analysis and debug of complex ASIC designs.
- RTL Design & Simulation: Write RTL (Register Transfer Level) code in Verilog or VHDL, and perform simulations using industry-standard tools like ModelSim, Cadence, or Synopsys.
- Design for Reliability: Focus on designing for high-reliability and radiation tolerance,
- Cross-Functional Collaboration: Collaborate with cross-functional teams like = hardware engineers, software engineers, and test engineers.
- Qualifications & Skills:
- Education: Bachelor's, Master's, or PhD degree in Electrical Engineering, Computer Engineering, or a related field.
- Experience:
- Minimum of 5-8 years of hands-on experience in ASIC design for aerospace, defense.
- Proven expertise in designing ASICs that meet high-reliability standards, such as MIL-STD-883, DO-254, or other aerospace-specific certifications.
- Solid understanding of digital design, RTL coding (Verilog/VHDL), and ASIC flow (synthesis, place & route, timing analysis).
- Experience with ASIC verification techniques (e.g., functional verification, simulation, emulation, DFT).
- Knowledge of radiation-hardened (Rad-Hard) or radiation-tolerant ASIC design principles is a plus.
- Technical Skills:
- Expertise in Verilog/ VHDL and experience with ASIC synthesis tools like Cadence Genus, Synopsys Design Compiler.
- Experience with simulation tools such as ModelSim, VCS, or Xilinx Vivado.
- Familiarity with timing analysis, power optimization, and signal integrity.
- Experience in FPGA/ASIC hybrid systems and custom digital logic development.
- Knowledge of PCB design principles and experience working with high-speed boards is a plus.
- Soft Skills:
- Excellent problem-solving and analytical skills, with the ability to troubleshoot complex system-level issues.
- Strong communication skills to interact with cross-functional teams, including engineers, management, and customers.
- Ability to work independently with minimal supervision, while also collaborating in a team-oriented environment.
- Detail-oriented and committed to maintaining high standards of quality, safety, and reliability.
- Preferred Previous Experience:
- Experience with space-based electronics or aerospace communications.
- Familiarity with ISO 9001, AS9100, or similar quality standards in aerospace.
- Background in radiation effects on electronics or space environmental testing.
- Familiarity with FPGA-based ASIC prototyping for aerospace applications.