Apple's Silicon Engineering team is looking for a highly skilled and motivated ASIC Design Engineer ... Knowledge of low-power design techniques and power optimization strategies.
Apple's Silicon Engineering team is looking for a highly skilled and motivated ASIC Design Engineer ... Knowledge of low-power design techniques and power optimization strategies.
ASIC Design Engineer
San Diego, CA · On-site
$100 - $125/hr
Qualcomm is seeking talented ASIC Design Engineers to join our growing SoC and ASIC Design ... Synthesis, low-power design, and multi-voltage domain work * Design methodology, flows, automation ...
ASIC Design Engineer
San Diego, CA · On-site
$100 - $125/hr
Qualcomm is seeking talented ASIC Design Engineers to join our growing SoC and ASIC Design ... Synthesis, low-power design, and multi-voltage domain work * Design methodology, flows, automation ...
ASIC Design Engineer
San Diego, CA · On-site
$100 - $125/hr
Qualcomm is seeking talented ASIC Design Engineers to join our growing SoC and ASIC Design ... data center technologies, low-power design, or silicon validation.Knowledge of modern SoC ...
ASIC Design Engineer
San Diego, CA · On-site
$100 - $125/hr
Qualcomm is seeking talented ASIC Design Engineers to join our growing SoC and ASIC Design ... data center technologies, low-power design, or silicon validation.Knowledge of modern SoC ...
ASIC Design Engineer
San Diego, CA · On-site
Qualcomm is seeking talented ASIC Design Engineers to join our growing SoC and ASIC Design ... Synthesis, low-power design, and multi-voltage domain work * Design methodology, flows, automation ...
ASIC Design Engineer
San Diego, CA · On-site
Qualcomm is seeking talented ASIC Design Engineers to join our growing SoC and ASIC Design ... Synthesis, low-power design, and multi-voltage domain work * Design methodology, flows, automation ...
Apple's Silicon Engineering team is looking for a highly skilled and motivated ASIC Design Engineer ... Knowledge of low-power design techniques and power optimization strategies.
Apple's Silicon Engineering team is looking for a highly skilled and motivated ASIC Design Engineer ... Knowledge of low-power design techniques and power optimization strategies.
Design Engineer (Low Power)
Santa Clara, CA · On-site
$176K - $264K/yr
... Low Power micro-architecture, Power Intent/Implementation, power estimates and power reduction ... The candidate will work hands-on and own their design through the full ASIC development process ...
Design Engineer (Low Power)
Santa Clara, CA · On-site
$176K - $264K/yr
... Low Power micro-architecture, Power Intent/Implementation, power estimates and power reduction ... The candidate will work hands-on and own their design through the full ASIC development process ...
Senior ASIC Design Engineer, Analog and Power, remote OK
Cincinnati, OH · Remote
$125K - $165K/yr
You will serve as the solo ASIC Design Engineer owning architecture, transistor‐level design ... low/high-voltage stages, and switching/linear regulators. * IP Development: Develop analog/power IP ...
Quick apply
Senior ASIC Design Engineer, Analog and Power, remote OK
Cincinnati, OH · Remote
$125K - $165K/yr
You will serve as the solo ASIC Design Engineer owning architecture, transistor‐level design ... low/high-voltage stages, and switching/linear regulators. * IP Development: Develop analog/power IP ...
ASIC Design Engineer Responsibilities: * Define and bring up FPGA platforms for pre-silicon ... Experience with validating and debugging low-power wireless systems * Understanding of common ...
Quick apply
ASIC Design Engineer Responsibilities: * Define and bring up FPGA platforms for pre-silicon ... Experience with validating and debugging low-power wireless systems * Understanding of common ...
Description As an ASIC Design Engineer in the Pixel IP design team, you will work closely with architecture, design, and verification teams to design high performance and low power pixel processing ...
Description As an ASIC Design Engineer in the Pixel IP design team, you will work closely with architecture, design, and verification teams to design high performance and low power pixel processing ...
Low Power Design/Methodology Engineer
San Diego, CA · On-site
$125 - $150/hr
Familiar with ASIC front-end design process and related flow, including u-arch, RTL coding ... Familiarity with advanced low power techniques and tools such as UPF, CLP, power aware DV and high ...
Low Power Design/Methodology Engineer
San Diego, CA · On-site
$125 - $150/hr
Familiar with ASIC front-end design process and related flow, including u-arch, RTL coding ... Familiarity with advanced low power techniques and tools such as UPF, CLP, power aware DV and high ...
Proficiency with UPF (Low power intent) * Proficiency in clock crossing techniques. * Knowledge of Static Timing Analysis and understanding of timing signoff fundamentals. What we are looking for:
Proficiency with UPF (Low power intent) * Proficiency in clock crossing techniques. * Knowledge of Static Timing Analysis and understanding of timing signoff fundamentals. What we are looking for:
Apple's Silicon Security team is looking for a driven ASIC Design Engineer to build the secure ... Familiarity with low-power design techniques and UPF (Unified Power Format). Solid understanding of ...
Apple's Silicon Security team is looking for a driven ASIC Design Engineer to build the secure ... Familiarity with low-power design techniques and UPF (Unified Power Format). Solid understanding of ...
Description As an ASIC Design Engineer in the Pixel IP design team, you be responsible for complex ... Experience in low-power design issues, tools, and methodologies including UPF power intent ...
Description As an ASIC Design Engineer in the Pixel IP design team, you be responsible for complex ... Experience in low-power design issues, tools, and methodologies including UPF power intent ...
Familiar with ASIC front-end design process and related flow, including u-arch, RTL coding ... Familiarity with advanced low power techniques and tools such as UPF, CLP, power aware DV and high ...
Familiar with ASIC front-end design process and related flow, including u-arch, RTL coding ... Familiarity with advanced low power techniques and tools such as UPF, CLP, power aware DV and high ...
Proficiency with UPF (Low power intent) * Proficiency in clock crossing techniques. * Knowledge of Static Timing Analysis and understanding of timing signoff fundamentals. What we are looking for:
Proficiency with UPF (Low power intent) * Proficiency in clock crossing techniques. * Knowledge of Static Timing Analysis and understanding of timing signoff fundamentals. What we are looking for:
Proficiency with UPF (Low power intent) * Proficiency in clock crossing techniques. * Knowledge of Static Timing Analysis and understanding of timing signoff fundamentals. What we are looking for:
Proficiency with UPF (Low power intent) * Proficiency in clock crossing techniques. * Knowledge of Static Timing Analysis and understanding of timing signoff fundamentals. What we are looking for:
ASIC Design Engineer -- IP Integration & Implementation
Sunnyvale, CA · On-site
$250/hr
DESCRIPTION As an ASIC Design Engineer in the Pixel IP design team, you be responsible for complex ... Experience in low-power design issues, tools, and methodologies including UPF power intent ...
ASIC Design Engineer -- IP Integration & Implementation
Sunnyvale, CA · On-site
$250/hr
DESCRIPTION As an ASIC Design Engineer in the Pixel IP design team, you be responsible for complex ... Experience in low-power design issues, tools, and methodologies including UPF power intent ...
ASIC Design Engineer
Santa Clara, CA · On-site
$150 - $200/hr
Bachelor's degree in Science, Engineering, or related field and 2+ years of ASIC design ... Low Power design and implementation * Chip interconnect (NOC) implementation Pay range and Other ...
ASIC Design Engineer
Santa Clara, CA · On-site
$150 - $200/hr
Bachelor's degree in Science, Engineering, or related field and 2+ years of ASIC design ... Low Power design and implementation * Chip interconnect (NOC) implementation Pay range and Other ...
Senior ASIC Design & Integration Engineer
Cupertino, CA · On-site
$200 - $250/hr
Apple's Silicon Engineering team is looking for a highly skilled and motivated ASIC Design Engineer ... Knowledge of low-power design techniques and power optimization strategies. Apple is an equal ...
Senior ASIC Design & Integration Engineer
Cupertino, CA · On-site
$200 - $250/hr
Apple's Silicon Engineering team is looking for a highly skilled and motivated ASIC Design Engineer ... Knowledge of low-power design techniques and power optimization strategies. Apple is an equal ...
ASIC Design and Integration Engineer
$150K - $277K/yr
Apple's Silicon Engineering team is looking for a highly skilled and motivated ASIC Design Engineer ... Knowledge of low-power design techniques and power optimization strategies. Minimum Qualifications ...
ASIC Design and Integration Engineer
$150K - $277K/yr
Apple's Silicon Engineering team is looking for a highly skilled and motivated ASIC Design Engineer ... Knowledge of low-power design techniques and power optimization strategies. Minimum Qualifications ...
Low Power Asic Design Engineer information
See salary details
$94K - $103.8K
16% of jobs
$103.8K - $113.6K
3% of jobs
$113.6K - $123.5K
4% of jobs
$126.3K is the 25th percentile. Wages below this are outliers.
$123.5K - $133.3K
6% of jobs
The median wage is $139.4K / yr.
$133.3K - $143.1K
33% of jobs
$143.1K - $152.9K
3% of jobs
$152.9K - $162.7K
2% of jobs
$169.2K is the 75th percentile. Wages above this are outliers.
$162.7K - $172.5K
12% of jobs
$172.5K - $182.4K
5% of jobs
$182.4K - $192.2K
4% of jobs
$192.2K - $202K
12% of jobs
$94K
$150.2K
$202K
How much do low power asic design engineer jobs pay per year?
As of Sep 9, 2026, the average yearly pay for low power asic design engineer in the United States is $150,195.00, according to ZipRecruiter salary data. Most workers in this role earn between $131,500.00 and $180,000.00 per year, depending on experience, location, and employer.
What does a low power ASIC design engineer do?
A Low Power ASIC Design Engineer specializes in designing Application-Specific Integrated Circuits (ASICs) with a focus on minimizing power consumption. They use various techniques at the architectural, circuit, and physical design levels to reduce both dynamic and static power, ensuring the chip meets performance and efficiency requirements. Their responsibilities often include power analysis, optimization, verification, and collaborating with other engineering teams throughout the design process. This role is crucial for developing chips used in battery-powered or energy-sensitive applications such as mobile devices, IoT, and wearable technology.
What are the key skills and qualifications needed to thrive as a low power ASIC design engineer?
To excel as a Low Power ASIC Design Engineer, you need a solid background in digital electronics, integrated circuit design, and power optimization techniques, often supported by a degree in electrical or computer engineering. Familiarity with EDA tools like Cadence, Synopsys, and power analysis tools, as well as experience with hardware description languages (HDLs) such as Verilog or VHDL, is typically required. Strong problem-solving, attention to detail, and effective collaboration skills help engineers navigate complex design challenges and work efficiently within multidisciplinary teams. These abilities are crucial for creating energy-efficient, high-performance ASICs that meet stringent power and functionality requirements in today's technology landscape.
What are some common challenges faced by low power ASIC design engineers when optimizing circuits for minimal energy consumption?
Low Power ASIC Design Engineers often encounter the challenge of balancing power efficiency with performance and area constraints. Achieving aggressive power targets may require employing advanced techniques like clock gating, multi-voltage domains, and power gating, which can add complexity to the design and verification process. Additionally, collaborating closely with cross-functional teams such as architecture, verification, and physical design is crucial to ensure that low power strategies do not negatively impact the overall functionality or manufacturability of the chip. Keeping up with evolving process technologies and power estimation tools is also essential to deliver successful low power ASIC solutions.
What is the difference between Low Power Asic Design Engineer vs Digital ASIC Design Engineer?
| Aspect | Low Power ASIC Design Engineer | Digital ASIC Design Engineer |
|---|---|---|
| Focus | Designing ASICs optimized for low power consumption | Designing digital ASICs with a focus on performance and functionality |
| Skills | Low power techniques, power analysis, low power verification | Digital logic design, RTL coding, verification |
| Work Environment | Semiconductor companies, chip design firms | Semiconductor companies, integrated circuit design firms |
| Certifications | ASIC design, low power design courses | ASIC design, digital design certifications |
While both roles involve ASIC design, the Low Power ASIC Design Engineer specializes in reducing power consumption, whereas the Digital ASIC Design Engineer focuses on digital logic and performance. The roles often overlap, but the primary distinction lies in the emphasis on power optimization versus digital functionality.
What are popular job titles related to Low Power Asic Design Engineer jobs?
For Low Power Asic Design Engineer jobs, the most frequently searched job titles are:
ASIC Design and Integration Engineer
Beaverton, OR • On-site
Apple •
Computer and Electronic Product Manufacturing • 10K+ employees10,000+ employees
Full-time
Re-posted 20 days ago
Apple rating
8.1
Based on 684 frontline employees who took The Breakroom Quiz
6th of 30 rated technology retailers
Job description
Apple's Silicon Engineering team is looking for a highly skilled and motivated ASIC Design Engineer to join our dynamic group. In this role, you will develop custom SoCs that drive the performance and efficiency of Apple's products. You will work on cutting-edge technologies and collaborate with cross-functional teams to deliver groundbreaking solutions.
Description
Design and Development: Design, implementation, and verification of complex ASICs. Develop RTL using SystemVerilog and perform synthesis.
Verification: Engage with simulation-based and formal verification teams to ensure robust design validation.
Integration and Testing: Collaborate with hardware and software teams to integrate digital designs into complex SoCs.
Timing and Power Analysis: Conduct timing analysis and power optimization to achieve PPA goals.
Documentation and Reporting: Create detailed micro-architecture and design documentation.
Minimum Qualifications
Minimum of BS + 10 years relevant industry experience
Preferred Qualifications
Experience: 8+ years of proven experience in ASIC design, including RTL design and verification. Hands-on experience with ASIC design tools and methodologies is essential.
Technical Skills: Proficiency in SystemVerilog, RTL design, synthesis, and timing analysis.
Problem-Solving: Strong analytical and problem-solving skills.
Collaboration: Excellent communication and teamwork skills, work effectively in cross-functional teams.
Attention to Detail: Meticulous attention to detail and a commitment to delivering high-quality designs.
Experience with high-speed I/O design and protocols. Knowledge of PCIe is a plus.
Familiarity with custom ASIC design and FPGA prototyping.
Hands on experience in all aspects of front-end chip development process (e.g., CDC/RDC, LINT, LEC, etc.).
Knowledge of low-power design techniques and power optimization strategies.
Description
Design and Development: Design, implementation, and verification of complex ASICs. Develop RTL using SystemVerilog and perform synthesis.
Verification: Engage with simulation-based and formal verification teams to ensure robust design validation.
Integration and Testing: Collaborate with hardware and software teams to integrate digital designs into complex SoCs.
Timing and Power Analysis: Conduct timing analysis and power optimization to achieve PPA goals.
Documentation and Reporting: Create detailed micro-architecture and design documentation.
Minimum Qualifications
Minimum of BS + 10 years relevant industry experience
Preferred Qualifications
Experience: 8+ years of proven experience in ASIC design, including RTL design and verification. Hands-on experience with ASIC design tools and methodologies is essential.
Technical Skills: Proficiency in SystemVerilog, RTL design, synthesis, and timing analysis.
Problem-Solving: Strong analytical and problem-solving skills.
Collaboration: Excellent communication and teamwork skills, work effectively in cross-functional teams.
Attention to Detail: Meticulous attention to detail and a commitment to delivering high-quality designs.
Experience with high-speed I/O design and protocols. Knowledge of PCIe is a plus.
Familiarity with custom ASIC design and FPGA prototyping.
Hands on experience in all aspects of front-end chip development process (e.g., CDC/RDC, LINT, LEC, etc.).
Knowledge of low-power design techniques and power optimization strategies.
About Apple
Sourced by ZipRecruiter
Imagine what you could do here! At Apple, new ideas have a way of becoming extraordinary products, services, and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could accomplish. Dynamic, intelligent people and inspiring, innovative technologies are the norm here. The people who work here have reinvented entire industries with all Apple Hardware products. The same real passion for innovation that goes into our products also applies to our practices strengthening our dedication to leave the world better than we found it.
Industry
Computer and electronic product manufacturing
Company size
10,000+ Employees
Headquarters location
Cupertino, CA, US
Year founded
1976