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Junior Vhdl Programmer Jobs (NOW HIRING)

... junior engineers and contribute to technical reviews. REQUIRED SKILLS * Strong proficiency in RTL design using Verilog/VHDL, including custom implementations beyond vendor IP integration. * Strong ...

Senior FPGA Design Engineer

Melbourne, FL · On-site

$145K - $175K/yr

... junior engineers and contribute to technical reviews. REQUIRED SKILLS * Strong proficiency in RTL design using Verilog/VHDL, including custom implementations beyond vendor IP integration. * Strong ...

Senior FPGA Design Engineer

Melbourne, FL · On-site

$145K - $175K/yr

... junior engineers and contribute to technical reviews. REQUIRED SKILLS * Strong proficiency in RTL design using Verilog/VHDL, including custom implementations beyond vendor IP integration. * Strong ...

... junior engineers and contribute to technical reviews. REQUIRED SKILLS * Strong proficiency in RTL design using Verilog/VHDL, including custom implementations beyond vendor IP integration. * Strong ...

$86.80 - $165.20/hr

  • Medical

  • Dental

  • Vision

  • Life

  • Retirement

  • PTO

Designs are implemented using VHDL for gigabit serial interfaces, radio frequency (RF) and ... Lead small teams and mentor junior engineers. * Support internal and external technical reviews.

Senior Electrical Engineer

Jessup, MD

$99K - $177K/yr

  • Medical

  • Dental

  • Vision

  • Retirement

Mentor and guide junior electrical engineers. Qualifications and Certifications * Bachelor's degree ... Verilog and VHDL experience preferred. * Ability to obtain security clearance. Benefits * Medical ...

Principal FPGA Engineer

Mckinney, TX · On-site

$107.50 - $204.50/hr

  • Medical

  • Dental

  • Vision

  • Life

  • Retirement

  • PTO

... junior engineers. Qualifications * Typically requires a STEM degree and a minimum of 8 years of prior relevant experience. * Experience with FPGA/ASIC design (VHDL and/or Verilog) or verification ...

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Junior Vhdl Programmer information

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How much do junior vhdl programmer jobs pay per hour?

As of Aug 15, 2026, the average hourly pay for junior vhdl programmer in the United States is $26.96, according to ZipRecruiter salary data. Most workers in this role earn between $16.35 and $33.17 per hour, depending on experience, location, and employer.

What is the difference between Junior Vhdl Programmer vs FPGA Engineer?

AspectJunior Vhdl ProgrammerFPGA Engineer
Required CredentialsBasic knowledge of VHDL, some programming experienceVHDL expertise, possibly additional FPGA design certifications
Work EnvironmentEntry-level, focused on coding and simulationDesign, testing, and implementation of FPGA systems
Industry UsageUsed in electronics and embedded systems companiesCommon in telecommunications, aerospace, and defense sectors
Search & Comparison IntentLooking for beginner-level VHDL rolesSeeking advanced FPGA design positions

The main difference between a Junior Vhdl Programmer and an FPGA Engineer lies in experience and scope. Junior Vhdl Programmers typically focus on coding and simulation tasks with basic VHDL knowledge, while FPGA Engineers handle comprehensive FPGA design, testing, and implementation, often requiring deeper expertise and certifications. Both roles are essential in electronics and embedded systems industries, but they differ in complexity and responsibility.

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Infographic showing various Junior Vhdl Programmer job openings in the United States as of August 2026, with employment types broken down into 85% Full Time, 5% Part Time, 9% Contract, and 1% Nights. Highlights an 89% Physical, 3% Hybrid, and 8% Remote job distribution, with an average salary of $56,068 per year, or $27 per hour.

Principal FPGA/ASIC Verification Engineer (Onsite)

Prattwhitney

Fort Wayne, IN • On-site

$90 - $120/hr

Other

Posted 10 days ago


Job description

Position Overview

Principal Electrical or Computer Engineer – Onsite, FortWayne, IN (US‑Citizen required). Requires an active and transferable U.S. government‑issued security clearance (DoD Secret). This role leads the design, implementation, and verification of advanced testbenches for a portfolio of high‑performance digital ASICs and FPGAs, supporting critical MissionSystems programs within the Microelectronics Technology team.

Responsibilities
  • Verification environment architecture and design using SystemVerilog with OVM/UVM
  • Creation of written test plan, test cases, code coverage tracking, and functional coverage tracking
  • Testbench development for the verification of RTL blocks using VHDL or SystemVerilog
  • Recommend new tools and practices for continuous improvement in the group’s ASIC/FPGA verification flow
  • Contribute to engineering estimates for new program pursuits
  • Provide technical leadership for project verification teams, breaking down work, planning activities, and reporting status
Qualifications
  • Typically requires a STEM degree and minimum 8years of relevant experience, or an advanced degree and minimum 5years of experience
  • Demonstrated experience developing and simulating RTL designs using VHDL and/or Verilog in a professional FPGA or ASIC development environment (at least 4years)
  • Proven ability to design, implement, and execute verification testbenches for RTL blocks using VHDL and/or SystemVerilog
  • Experience with chip‑level verification methodologies (constrained‑random testing, functional coverage analysis, assertion‑based verification)
  • Experience using revision control systems such as Git or Subversion
  • Demonstrated ability to work independently and mentor junior engineers
  • Preferred: Experience with ASIC/FPGA lab validation and debug, familiarity with DFT, manufacturability, and production test concepts, proficiency with Unix/Linux, scripting or software development
Security Clearance

U.S. citizenship required. Active and transferable DoD Secret security clearance required prior to start date.

EEO Statement

RTX is an Equal Opportunity Employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, age, disability or veteran status.

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