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Junior Rtl Design Engineer Jobs in Mundelein, IL

Eliyan

Digital - SerDes Digital Design Lead

Mundelein, IL

$138K/yr

... Engineering, or related fields * 12+ years of experience in digital design of high-speed SerDes, PHY, or transceiver IPs with proven tapeout experience at 112G PAM4 or higher data rates * Strong RTL ...

Edgehog Trading

Junior FPGA Developer

Chicago, IL · On-site

$100 - $175/hr

Our team spans trading, engineering, and business operations, working together to build and support ... Design, implement, and verify RTL logic in Verilog or SystemVerilog targeting ultra-low-latency ...

Edgehog Trading

Junior FPGA Developer

Chicago, IL · On-site

Our team spans trading, engineering, and business operations, working together to build and support ... Design, implement, and verify RTL logic in Verilog or SystemVerilog targeting ultra-low-latency ...

IMC

Hardware Engineer

Chicago, IL

$127K - $167K/yr

IMC is seeking a Hardware Engineer to join our Global Hardware team and help develop the next ... Design and implement RTL for next-generation ASIC platforms using SystemVerilog * Contribute to ...

IMC

Hardware Engineer

Chicago, IL · On-site

$127K - $167K/yr

IMC is seeking a Hardware Engineer to join our Global Hardware team and help develop the next ... Design and implement RTL for next-generation ASIC platforms using SystemVerilog * Contribute to ...

IMC

Hardware Engineer

Chicago, IL · On-site

$127K - $168K/yr

IMC is seeking a Hardware Engineer to join our Global Hardware team and help develop the next ... Design and implement RTL for next-generation ASIC platforms using SystemVerilog * Contribute to ...

Del Medical

Mechanical Design Engineer

Bloomingdale, IL · On-site

$80 - $100/hr

Guide junior engineers through projects, offering mentorship, training, and support to foster a ... Design for Manufacturability: Ensure designs are optimized for cost‑effective and efficient ...

Ashby

Design Engineer - Americas

Chicago, IL · Remote

$126K - $250K/yr

Junior Design Engineer - You should have no more than 2 years of industry experience as a designer or engineer. We want to see projects (personal or professional) with at least a couple of users that ...

SWE Solutions

Design Engineer II

Chicago, IL · On-site

$38 - $51/hr

We are looking for an experienced Civil Design Engineer II to join our dynamic team and take a ... Oversee and review the work of junior engineers and designers to ensure accuracy and quality.

SWE Solutions

Design Engineer II

Chicago, IL · On-site

$38 - $51/hr

Oversee and review the work of junior engineers and designers to ensure accuracy and quality ... Proficiency in AutoCAD Civil 3D or similar design software. * Strong understanding of civil ...

SWE Solutions

Design Engineer II

Chicago, IL · On-site

$38 - $51/hr

Oversee and review the work of junior engineers and designers to ensure accuracy and quality ... Proficiency in AutoCAD Civil 3D or similar design software. * Strong understanding of civil ...

IEA

Senior Design Engineer

Kenosha, WI · On-site

The Sr. Design Engineer will mentor the Design Engineers and Jr. Design Engineers. Essential Duties and Responsibilities: Design heat transfer products for Engendren. This may include radiator-based ...

Luxus

Senior Design Engineer - Bridge

West Chicago, IL · Hybrid

$85K - $115K/yr

Senior Design Engineer - Bridge Location: Chicago, IL (Hybrid - Flexible Schedule, Partial Remote ... You'll work directly with multi-disciplinary teams, lead technical execution, mentor junior staff ...

Luxus

Senior Design Engineer - Bridge

West Chicago, IL · Hybrid

$85K - $115K/yr

Senior Design Engineer - Bridge Location: Chicago, IL (Hybrid - Flexible Schedule, Partial Remote ... You'll work directly with multi-disciplinary teams, lead technical execution, mentor junior staff ...

Luxus

Senior Design Engineer - Bridge

West Chicago, IL · On-site

$85K - $115K/yr

Senior Design Engineer - Bridge Location: Chicago, IL (Hybrid - Flexible Schedule, Partial Remote ... You'll work directly with multi-disciplinary teams, lead technical execution, mentor junior staff ...

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All JobsRtl Design Engineer JobsJunior Rtl Design Engineer JobsJunior Rtl Design Engineer Jobs in Mundelein, IL

Junior Rtl Design Engineer information

See Mundelein, IL salary details

$34.2K

$73.3K

$111.8K

How much do junior rtl design engineer jobs pay per year?

As of Aug 23, 2026, the average yearly pay for junior rtl design engineer in Mundelein, IL is $73,301.00, according to ZipRecruiter salary data. Most workers in this role earn between $49,500.00 and $81,700.00 per year, depending on experience, location, and employer.

What is a junior RTL design engineer?

Junior RTL Design Engineers are entry-level professionals who work on designing and verifying the Register Transfer Level (RTL) logic for digital integrated circuits. They typically use hardware description languages like Verilog or VHDL to describe and simulate the functionality of hardware blocks according to specifications. Their responsibilities often include coding, simulation, debugging, and collaborating with senior engineers to ensure the design meets performance and functional requirements. This role is crucial in the process of creating chips and digital systems used in various electronic devices.

What are the key skills and qualifications needed to thrive as a junior RTL design engineer?

To thrive as a Junior RTL Design Engineer, a solid background in digital logic design, hardware description languages (such as Verilog or VHDL), and a relevant engineering degree are essential. Experience with simulation and synthesis tools (like ModelSim, Synopsys, or Xilinx Vivado) and a basic understanding of ASIC or FPGA flows are typically required. Strong analytical thinking, attention to detail, and effective teamwork skills help individuals excel in translating specifications into efficient hardware designs. These skills ensure accurate, reliable, and high-performance digital circuit development, which is crucial for meeting project goals and industry standards.

What are some common challenges faced by junior RTL design engineers when transitioning from academic projects to industry roles?

Junior RTL Design Engineers often find the transition from academic projects to industry roles challenging due to the increased complexity and scale of commercial designs. In industry, there is a strong emphasis on meeting strict timing, power, and area requirements, as well as adhering to rigorous verification and documentation standards. Collaboration with verification, physical design, and software teams is essential, and juniors may need to quickly adapt to using industry-standard EDA tools and workflows. Gaining proficiency in debugging and understanding legacy codebases are also typical hurdles. However, most teams provide mentorship and structured onboarding to help new engineers succeed.

What is the difference between Junior Rtl Design Engineer vs Digital Design Engineer?

AspectJunior Rtl Design EngineerDigital Design Engineer
Required CredentialsBachelor's in Electrical Engineering or related field; some certificationsBachelor's or higher in Electrical/Electronic Engineering; certifications vary
Work EnvironmentDesign teams in semiconductor or electronics companiesDesign and development teams in similar industries
Employer & Industry UsageCommonly employed in chip design, FPGA, ASIC developmentUsed in digital circuit and system design across industries

Both roles involve digital circuit design, but Junior Rtl Design Engineers focus more on RTL coding and verification, while Digital Design Engineers may handle broader digital system development. The roles often overlap in skills and work environment, with the main difference being scope and experience level.

What are popular job titles related to Junior Rtl Design Engineer jobs in Mundelein, IL?

For Junior Rtl Design Engineer jobs in Mundelein, IL, the most frequently searched job titles are:

What job categories do people searching Junior Rtl Design Engineer jobs in Mundelein, IL look for?

The top searched job categories for Junior Rtl Design Engineer jobs in Mundelein, IL are:

What cities near Mundelein, IL are hiring for Junior Rtl Design Engineer jobs?

Cities near Mundelein, IL with the most Junior Rtl Design Engineer job openings:

Junior Rtl Design Engineer jobs near you
Infographic showing various Junior Rtl Design Engineer job openings in Mundelein, IL as of August 2026, with employment types broken down into 87% Full Time, 8% Part Time, and 5% Contract. Highlights an 85% Physical, 4% Hybrid, and 11% Remote job distribution, with an average salary of $73,301 per year, or $35.2 per hour.

Digital - SerDes Digital Design Lead

Eliyan

Mundelein, IL

$138K/yr

Full-time

Re-posted 3 days ago

Job description

Join the leading chiplet startup!  As the SerDes Digital Design Lead at Eliyan, you will drive the architecture and implementation of next-generation high-speed serial link IPs targeting 224G and 448G data rates for chiplet-based systems with best-in-class power, area, manufacturability, and design flexibility.  You will lead the digital design of SerDes transmitter and receiver datapaths, clock and data recovery (CDR) digital logic, equalization engines, and PHY-level controller logic for cutting-edge interconnect products.  You will work with a cross-functional team of experts that operate from first principles, innovate and push the envelope to create high-volume and high-performance manufacturable products.  We offer a fun work environment with excellent benefits.
Key Responsibilities:
  • Lead the micro-architecture definition and RTL implementation of high-speed SerDes digital blocks targeting 224G PAM4 and 448G signaling, including DSP-based equalization (FFE, DFE, CTLE digital controls), CDR loop logic, and adaptation engines
  • Design and optimize PHY-level digital logic including TX driver control, RX datapath, PCS sublayers, lane alignment, deskew, and gear-boxing/rate-matching logic
  • Architect and implement forward error correction (FEC) encoder/decoder blocks including RS-FEC (KP4/KP8), interleaving, and low-latency FEC architectures optimized for 224G/448G link budgets
  • Drive RTL design quality through lint, CDC/RDC analysis, synthesis optimization, and close collaboration with physical design and timing closure teams on advanced FinFET/GAA process nodes
  • Collaborate closely with analog/mixed-signal designers on SerDes AFE integration, digital-to-analog interface specification, calibration sequencing, and AMS co-simulation bring-up
  • Own design deliverables and milestones from RTL development through tapeout signoff; coordinate with verification, DFT, and backend teams to meet aggressive schedules
  • Define and implement auto-negotiation, link training, and PHY initialization state machines compliant with IEEE 802.3
  • Develop power-efficient digital architectures with emphasis on clock gating, voltage scaling, and low-power design techniques for data center and AI/ML interconnect applications
  • Participate in standards bodies and stay current with emerging 224G/448G specifications, OIF CEI, and next-generation interconnect standards
  • Design firmware-accessible register interfaces, configuration/calibration logic, and DPI-based firmware co-simulation hooks for PHY bring-up and debug
  • Support post-silicon characterization and debug activities; correlate silicon measurements with pre-silicon simulation results to drive design improvements
Qualifications:
  • Masters or Ph.D in Electrical Engineering, Computer Engineering, or related fields
  • 12+ years of experience in digital design of high-speed SerDes, PHY, or transceiver IPs with proven tapeout experience at 112G PAM4 or higher data rates
  • Strong RTL design skills in SystemVerilog with deep understanding of synthesis, timing closure, CDC/RDC, and design-for-test (DFT) methodologies
  • Expert-level knowledge of SerDes DSP architectures including FFE, DFE, MLSE, CTLE digital controls, CDR loop dynamics, and adaptation/calibration algorithms for PAM4 signaling
  • Strong working knowledge of IEEE 802.3 (100G/200G/400G/800G/1.6T), OIF CEI specifications, FEC architectures (RS-FEC KP4/KP8), and/or die-to-die standards such as UCIe
  • Hands-on experience with high-speed digital design on advanced process nodes (5nm, 3nm, or below) with understanding of FinFET/GAA device implications on circuit performance and power
  • Experience working at the digital-analog boundary including specification of DAC/ADC interfaces, calibration state machines, and integration with mixed-signal simulation environments
  • Demonstrated technical leadership with ability to mentor engineers, drive architectural decisions, and deliver silicon on aggressive schedules in startup or high-growth environments
  • Experience with optical/electrical interconnects (VCSEL, EML), chiplet D2D interfaces, DRAM PHYs, or HBM memory interfaces a plus

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