... Engineering, or related fields * 12+ years of experience in digital design of high-speed SerDes, PHY, or transceiver IPs with proven tapeout experience at 112G PAM4 or higher data rates * Strong RTL ...
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... Engineering, or related fields * 12+ years of experience in digital design of high-speed SerDes, PHY, or transceiver IPs with proven tapeout experience at 112G PAM4 or higher data rates * Strong RTL ...
Junior FPGA Developer
Chicago, IL · On-site
Our team spans trading, engineering, and business operations, working together to build and support ... Design, implement, and verify RTL logic in Verilog or SystemVerilog targeting ultra-low-latency ...
Junior FPGA Developer
Chicago, IL · On-site
Our team spans trading, engineering, and business operations, working together to build and support ... Design, implement, and verify RTL logic in Verilog or SystemVerilog targeting ultra-low-latency ...
Hardware Engineer
Chicago, IL · On-site
$127K - $168K/yr
IMC is seeking a Hardware Engineer to join our Global Hardware team and help develop the next ... Design and implement RTL for next-generation ASIC platforms using SystemVerilog * Contribute to ...
Hardware Engineer
Chicago, IL · On-site
$127K - $168K/yr
IMC is seeking a Hardware Engineer to join our Global Hardware team and help develop the next ... Design and implement RTL for next-generation ASIC platforms using SystemVerilog * Contribute to ...
Hardware Engineer
Chicago, IL · On-site
$127K - $167K/yr
IMC is seeking a Hardware Engineer to join our Global Hardware team and help develop the next ... Design and implement RTL for next-generation ASIC platforms using SystemVerilog * Contribute to ...
Hardware Engineer
Chicago, IL · On-site
$127K - $167K/yr
IMC is seeking a Hardware Engineer to join our Global Hardware team and help develop the next ... Design and implement RTL for next-generation ASIC platforms using SystemVerilog * Contribute to ...
Hardware Engineer
Chicago, IL · On-site
$127K - $167K/yr
IMC is seeking a Hardware Engineer to join our Global Hardware team and help develop the next ... Design and implement RTL for next-generation ASIC platforms using SystemVerilog * Contribute to ...
Hardware Engineer
Chicago, IL · On-site
$127K - $167K/yr
IMC is seeking a Hardware Engineer to join our Global Hardware team and help develop the next ... Design and implement RTL for next-generation ASIC platforms using SystemVerilog * Contribute to ...
Design Engineer - Americas
Chicago, IL · Remote
$126K - $250K/yr
Junior Design Engineer - You should have no more than 2 years of industry experience as a designer or engineer. We want to see projects (personal or professional) with at least a couple of users that ...
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Design Engineer - Americas
Chicago, IL · Remote
$126K - $250K/yr
Junior Design Engineer - You should have no more than 2 years of industry experience as a designer or engineer. We want to see projects (personal or professional) with at least a couple of users that ...
Design Engineer
Westmont, IL · On-site
$82K - $124K/yr
Mentor junior engineers and review work from designers and outside consultants * Develop or improve ... Design & Innovation * Root Cause Analysis & Problem Solving * Project Management * Professional ...
Design Engineer
Westmont, IL · On-site
$82K - $124K/yr
Mentor junior engineers and review work from designers and outside consultants * Develop or improve ... Design & Innovation * Root Cause Analysis & Problem Solving * Project Management * Professional ...
Design Engineer II
Chicago, IL · On-site
$38 - $51/hr
We are looking for an experienced Civil Design Engineer II to join our dynamic team and take a ... Oversee and review the work of junior engineers and designers to ensure accuracy and quality.
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Design Engineer II
Chicago, IL · On-site
$38 - $51/hr
We are looking for an experienced Civil Design Engineer II to join our dynamic team and take a ... Oversee and review the work of junior engineers and designers to ensure accuracy and quality.
SR Design Engineer
Wheaton, IL · On-site +1
$135K - $160K/yr
Title: Senior Design Engineer - Electric Distribution Location: Remote/Wheaton, IL Hire Type ... Mentor junior engineers and contribute to engineering standards, best practices, and technical ...
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SR Design Engineer
Wheaton, IL · On-site +1
$135K - $160K/yr
Title: Senior Design Engineer - Electric Distribution Location: Remote/Wheaton, IL Hire Type ... Mentor junior engineers and contribute to engineering standards, best practices, and technical ...
Design Engineer II
Chicago, IL · On-site
$38 - $51/hr
Oversee and review the work of junior engineers and designers to ensure accuracy and quality ... Proficiency in AutoCAD Civil 3D or similar design software. * Strong understanding of civil ...
Design Engineer II
Chicago, IL · On-site
$38 - $51/hr
Oversee and review the work of junior engineers and designers to ensure accuracy and quality ... Proficiency in AutoCAD Civil 3D or similar design software. * Strong understanding of civil ...
Design Engineer II
$38 - $51/hr
Oversee and review the work of junior engineers and designers to ensure accuracy and quality ... Proficiency in AutoCAD Civil 3D or similar design software. * Strong understanding of civil ...
Design Engineer II
$38 - $51/hr
Oversee and review the work of junior engineers and designers to ensure accuracy and quality ... Proficiency in AutoCAD Civil 3D or similar design software. * Strong understanding of civil ...
Senior Design Engineer - Bridge
West Chicago, IL · Hybrid
$85K - $115K/yr
Senior Design Engineer - Bridge Location: Chicago, IL (Hybrid - Flexible Schedule, Partial Remote ... You'll work directly with multi-disciplinary teams, lead technical execution, mentor junior staff ...
Senior Design Engineer - Bridge
West Chicago, IL · Hybrid
$85K - $115K/yr
Senior Design Engineer - Bridge Location: Chicago, IL (Hybrid - Flexible Schedule, Partial Remote ... You'll work directly with multi-disciplinary teams, lead technical execution, mentor junior staff ...
Senior Design Engineer - Bridge
West Chicago, IL · Hybrid
$85K - $115K/yr
Senior Design Engineer - Bridge Location: Chicago, IL (Hybrid - Flexible Schedule, Partial Remote ... You'll work directly with multi-disciplinary teams, lead technical execution, mentor junior staff ...
Senior Design Engineer - Bridge
West Chicago, IL · Hybrid
$85K - $115K/yr
Senior Design Engineer - Bridge Location: Chicago, IL (Hybrid - Flexible Schedule, Partial Remote ... You'll work directly with multi-disciplinary teams, lead technical execution, mentor junior staff ...
Senior Design Engineer - Bridge
West Chicago, IL · On-site
$85K - $115K/yr
Senior Design Engineer - Bridge Location: Chicago, IL (Hybrid - Flexible Schedule, Partial Remote ... You'll work directly with multi-disciplinary teams, lead technical execution, mentor junior staff ...
Senior Design Engineer - Bridge
West Chicago, IL · On-site
$85K - $115K/yr
Senior Design Engineer - Bridge Location: Chicago, IL (Hybrid - Flexible Schedule, Partial Remote ... You'll work directly with multi-disciplinary teams, lead technical execution, mentor junior staff ...
PD - Sr Staff -- CAD & Design Methodology \u007C RTL-to-GDSII Flow \u007C Advanced Node Methodology
Mundelein, IL · On-site
ABOUT THE ROLE As a Sr Staff / Principal CAD & Design Methodology Engineer , you will be the technical architect of RTL-to-GDSII flows and digital design infrastructure for advanced SoC products. You ...
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PD - Sr Staff -- CAD & Design Methodology \u007C RTL-to-GDSII Flow \u007C Advanced Node Methodology
Mundelein, IL · On-site
ABOUT THE ROLE As a Sr Staff / Principal CAD & Design Methodology Engineer , you will be the technical architect of RTL-to-GDSII flows and digital design infrastructure for advanced SoC products. You ...
As an FPGA Design Engineer, you will join our diverse team and be responsible for research ... Proficient in FPGA design flow including items such as RTL/gate level simulation, synthesis, place ...
As an FPGA Design Engineer, you will join our diverse team and be responsible for research ... Proficient in FPGA design flow including items such as RTL/gate level simulation, synthesis, place ...
Design Engineer
Downers Grove, IL · On-site
$72K - $95K/yr
PRODUCT DESIGN AND DEVELOPMENT * * Serve as the technical liaison with the customer. Clearly define ... Coach and train junior engineers, application engineers, and other engineering team members to help ...
Design Engineer
Downers Grove, IL · On-site
$72K - $95K/yr
PRODUCT DESIGN AND DEVELOPMENT * * Serve as the technical liaison with the customer. Clearly define ... Coach and train junior engineers, application engineers, and other engineering team members to help ...
Design Engineer
Downers Grove, IL · On-site +1
$72K - $95K/yr
PRODUCT DESIGN AND DEVELOPMENT * * Serve as the technical liaison with the customer. Clearly define ... Coach and train junior engineers, application engineers, and other engineering team members to help ...
Design Engineer
Downers Grove, IL · On-site +1
$72K - $95K/yr
PRODUCT DESIGN AND DEVELOPMENT * * Serve as the technical liaison with the customer. Clearly define ... Coach and train junior engineers, application engineers, and other engineering team members to help ...
As an FPGA Design Engineer, you will join our diverse team and be responsible for research ... Proficient in FPGA design flow including items such as RTL/gate level simulation, synthesis, place ...
As an FPGA Design Engineer, you will join our diverse team and be responsible for research ... Proficient in FPGA design flow including items such as RTL/gate level simulation, synthesis, place ...
Design Engineer
Downers Grove, IL · On-site +1
$72K - $95K/yr
PRODUCT DESIGN AND DEVELOPMENT * * Serve as the technical liaison with the customer. Clearly define ... Coach and train junior engineers, application engineers, and other engineering team members to help ...
Design Engineer
Downers Grove, IL · On-site +1
$72K - $95K/yr
PRODUCT DESIGN AND DEVELOPMENT * * Serve as the technical liaison with the customer. Clearly define ... Coach and train junior engineers, application engineers, and other engineering team members to help ...
Junior Rtl Design Engineer information
See Northfield, IL salary details
$34.8K - $41.9K
3% of jobs
$41.9K - $49.1K
20% of jobs
$50.7K is the 25th percentile. Wages below this are outliers.
$49.1K - $56.3K
7% of jobs
$56.3K - $63.5K
6% of jobs
$63.5K - $70.6K
12% of jobs
The median wage is $71.1K / yr.
$70.6K - $77.8K
17% of jobs
$81.6K is the 75th percentile. Wages above this are outliers.
$77.8K - $85K
17% of jobs
$85K - $92.2K
7% of jobs
$92.2K - $99.3K
4% of jobs
$99.3K - $106.5K
3% of jobs
$106.5K - $113.7K
2% of jobs
$34.8K
$74.5K
$113.7K
How much do junior rtl design engineer jobs pay per year?
As of Aug 18, 2026, the average yearly pay for junior rtl design engineer in Northfield, IL is $74,536.00, according to ZipRecruiter salary data. Most workers in this role earn between $50,300.00 and $83,000.00 per year, depending on experience, location, and employer.
What is a junior RTL design engineer?
Junior RTL Design Engineers are entry-level professionals who work on designing and verifying the Register Transfer Level (RTL) logic for digital integrated circuits. They typically use hardware description languages like Verilog or VHDL to describe and simulate the functionality of hardware blocks according to specifications. Their responsibilities often include coding, simulation, debugging, and collaborating with senior engineers to ensure the design meets performance and functional requirements. This role is crucial in the process of creating chips and digital systems used in various electronic devices.
What are the key skills and qualifications needed to thrive as a junior RTL design engineer?
To thrive as a Junior RTL Design Engineer, a solid background in digital logic design, hardware description languages (such as Verilog or VHDL), and a relevant engineering degree are essential. Experience with simulation and synthesis tools (like ModelSim, Synopsys, or Xilinx Vivado) and a basic understanding of ASIC or FPGA flows are typically required. Strong analytical thinking, attention to detail, and effective teamwork skills help individuals excel in translating specifications into efficient hardware designs. These skills ensure accurate, reliable, and high-performance digital circuit development, which is crucial for meeting project goals and industry standards.
What are some common challenges faced by junior RTL design engineers when transitioning from academic projects to industry roles?
Junior RTL Design Engineers often find the transition from academic projects to industry roles challenging due to the increased complexity and scale of commercial designs. In industry, there is a strong emphasis on meeting strict timing, power, and area requirements, as well as adhering to rigorous verification and documentation standards. Collaboration with verification, physical design, and software teams is essential, and juniors may need to quickly adapt to using industry-standard EDA tools and workflows. Gaining proficiency in debugging and understanding legacy codebases are also typical hurdles. However, most teams provide mentorship and structured onboarding to help new engineers succeed.
What is the difference between Junior Rtl Design Engineer vs Digital Design Engineer?
| Aspect | Junior Rtl Design Engineer | Digital Design Engineer |
|---|---|---|
| Required Credentials | Bachelor's in Electrical Engineering or related field; some certifications | Bachelor's or higher in Electrical/Electronic Engineering; certifications vary |
| Work Environment | Design teams in semiconductor or electronics companies | Design and development teams in similar industries |
| Employer & Industry Usage | Commonly employed in chip design, FPGA, ASIC development | Used in digital circuit and system design across industries |
Both roles involve digital circuit design, but Junior Rtl Design Engineers focus more on RTL coding and verification, while Digital Design Engineers may handle broader digital system development. The roles often overlap in skills and work environment, with the main difference being scope and experience level.
What job categories do people searching Junior Rtl Design Engineer jobs in Northfield, IL look for?
The top searched job categories for Junior Rtl Design Engineer jobs in Northfield, IL are:
What cities near Northfield, IL are hiring for Junior Rtl Design Engineer jobs?
Cities near Northfield, IL with the most Junior Rtl Design Engineer job openings:
$138K/yr
Full-time
Re-posted 28 days ago
Job description
Join the leading chiplet startup! As the SerDes Digital Design Lead at Eliyan, you will drive the architecture and implementation of next-generation high-speed serial link IPs targeting 224G and 448G data rates for chiplet-based systems with best-in-class power, area, manufacturability, and design flexibility. You will lead the digital design of SerDes transmitter and receiver datapaths, clock and data recovery (CDR) digital logic, equalization engines, and PHY-level controller logic for cutting-edge interconnect products. You will work with a cross-functional team of experts that operate from first principles, innovate and push the envelope to create high-volume and high-performance manufacturable products. We offer a fun work environment with excellent benefits.
Key Responsibilities:- Lead the micro-architecture definition and RTL implementation of high-speed SerDes digital blocks targeting 224G PAM4 and 448G signaling, including DSP-based equalization (FFE, DFE, CTLE digital controls), CDR loop logic, and adaptation engines
- Design and optimize PHY-level digital logic including TX driver control, RX datapath, PCS sublayers, lane alignment, deskew, and gear-boxing/rate-matching logic
- Architect and implement forward error correction (FEC) encoder/decoder blocks including RS-FEC (KP4/KP8), interleaving, and low-latency FEC architectures optimized for 224G/448G link budgets
- Drive RTL design quality through lint, CDC/RDC analysis, synthesis optimization, and close collaboration with physical design and timing closure teams on advanced FinFET/GAA process nodes
- Collaborate closely with analog/mixed-signal designers on SerDes AFE integration, digital-to-analog interface specification, calibration sequencing, and AMS co-simulation bring-up
- Own design deliverables and milestones from RTL development through tapeout signoff; coordinate with verification, DFT, and backend teams to meet aggressive schedules
- Define and implement auto-negotiation, link training, and PHY initialization state machines compliant with IEEE 802.3
- Develop power-efficient digital architectures with emphasis on clock gating, voltage scaling, and low-power design techniques for data center and AI/ML interconnect applications
- Participate in standards bodies and stay current with emerging 224G/448G specifications, OIF CEI, and next-generation interconnect standards
- Design firmware-accessible register interfaces, configuration/calibration logic, and DPI-based firmware co-simulation hooks for PHY bring-up and debug
- Support post-silicon characterization and debug activities; correlate silicon measurements with pre-silicon simulation results to drive design improvements
- Masters or Ph.D in Electrical Engineering, Computer Engineering, or related fields
- 12+ years of experience in digital design of high-speed SerDes, PHY, or transceiver IPs with proven tapeout experience at 112G PAM4 or higher data rates
- Strong RTL design skills in SystemVerilog with deep understanding of synthesis, timing closure, CDC/RDC, and design-for-test (DFT) methodologies
- Expert-level knowledge of SerDes DSP architectures including FFE, DFE, MLSE, CTLE digital controls, CDR loop dynamics, and adaptation/calibration algorithms for PAM4 signaling
- Strong working knowledge of IEEE 802.3 (100G/200G/400G/800G/1.6T), OIF CEI specifications, FEC architectures (RS-FEC KP4/KP8), and/or die-to-die standards such as UCIe
- Hands-on experience with high-speed digital design on advanced process nodes (5nm, 3nm, or below) with understanding of FinFET/GAA device implications on circuit performance and power
- Experience working at the digital-analog boundary including specification of DAC/ADC interfaces, calibration state machines, and integration with mixed-signal simulation environments
- Demonstrated technical leadership with ability to mentor engineers, drive architectural decisions, and deliver silicon on aggressive schedules in startup or high-growth environments
- Experience with optical/electrical interconnects (VCSEL, EML), chiplet D2D interfaces, DRAM PHYs, or HBM memory interfaces a plus
We may use artificial intelligence (AI) tools to support parts of the hiring process, such as reviewing applications, analyzing resumes, or assessing responses and identifying potential inconsistencies or verification signals in application materials based on available information. These tools assist our recruitment team but do not replace human judgment. Final hiring decisions are ultimately made by humans. If you would like more information about how your data is processed, please contact us.