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Junior Rtl Design Engineer Jobs in Missouri (NOW HIRING)

ArchPoint

Lead Substation Design Engineer

Saint Louis, MO · On-site

$120 - $180/hr

We are looking for a Lead Substation Design Engineer who can take ownership of substation design ... Prior experience mentoring junior engineers or designers-preferred * Professional Engineer license ...

WSP

Experienced Substation Design Engineer

Saint Louis, MO · On-site +1

$92K - $117K/yr

... mentoring junior staff. This position offers the opportunity to thrive in a fast-paced ... Perform professional electrical engineering work relating to the design of substation physical ...

WSP

Experienced Substation Design Engineer

Saint Louis, MO · On-site

$92K - $117K/yr

... mentoring junior staff. This position offers the opportunity to thrive in a fast-paced ... Perform professional electrical engineering work relating to the design of substation physical ...

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All JobsRtl Design Engineer JobsJunior Rtl Design Engineer JobsJunior Rtl Design Engineer Jobs in Missouri

Junior Rtl Design Engineer information

See Missouri salary details

$31.4K

$67.3K

$102.7K

How much do junior rtl design engineer jobs pay per year?

As of Aug 22, 2026, the average yearly pay for junior rtl design engineer in Missouri is $67,348.00, according to ZipRecruiter salary data. Most workers in this role earn between $45,500.00 and $75,000.00 per year, depending on experience, location, and employer.

What is a junior RTL design engineer?

Junior RTL Design Engineers are entry-level professionals who work on designing and verifying the Register Transfer Level (RTL) logic for digital integrated circuits. They typically use hardware description languages like Verilog or VHDL to describe and simulate the functionality of hardware blocks according to specifications. Their responsibilities often include coding, simulation, debugging, and collaborating with senior engineers to ensure the design meets performance and functional requirements. This role is crucial in the process of creating chips and digital systems used in various electronic devices.

What are the key skills and qualifications needed to thrive as a junior RTL design engineer?

To thrive as a Junior RTL Design Engineer, a solid background in digital logic design, hardware description languages (such as Verilog or VHDL), and a relevant engineering degree are essential. Experience with simulation and synthesis tools (like ModelSim, Synopsys, or Xilinx Vivado) and a basic understanding of ASIC or FPGA flows are typically required. Strong analytical thinking, attention to detail, and effective teamwork skills help individuals excel in translating specifications into efficient hardware designs. These skills ensure accurate, reliable, and high-performance digital circuit development, which is crucial for meeting project goals and industry standards.

What are some common challenges faced by junior RTL design engineers when transitioning from academic projects to industry roles?

Junior RTL Design Engineers often find the transition from academic projects to industry roles challenging due to the increased complexity and scale of commercial designs. In industry, there is a strong emphasis on meeting strict timing, power, and area requirements, as well as adhering to rigorous verification and documentation standards. Collaboration with verification, physical design, and software teams is essential, and juniors may need to quickly adapt to using industry-standard EDA tools and workflows. Gaining proficiency in debugging and understanding legacy codebases are also typical hurdles. However, most teams provide mentorship and structured onboarding to help new engineers succeed.

What is the difference between Junior Rtl Design Engineer vs Digital Design Engineer?

AspectJunior Rtl Design EngineerDigital Design Engineer
Required CredentialsBachelor's in Electrical Engineering or related field; some certificationsBachelor's or higher in Electrical/Electronic Engineering; certifications vary
Work EnvironmentDesign teams in semiconductor or electronics companiesDesign and development teams in similar industries
Employer & Industry UsageCommonly employed in chip design, FPGA, ASIC developmentUsed in digital circuit and system design across industries

Both roles involve digital circuit design, but Junior Rtl Design Engineers focus more on RTL coding and verification, while Digital Design Engineers may handle broader digital system development. The roles often overlap in skills and work environment, with the main difference being scope and experience level.

What are popular job titles related to Junior Rtl Design Engineer jobs in Missouri?

For Junior Rtl Design Engineer jobs in Missouri, the most frequently searched job titles are:

What job categories do people searching Junior Rtl Design Engineer jobs in Missouri look for?

The top searched job categories for Junior Rtl Design Engineer jobs in Missouri are:

What cities in Missouri are hiring for Junior Rtl Design Engineer jobs?

Cities in Missouri with the most Junior Rtl Design Engineer job openings:

Junior Rtl Design Engineer jobs near you
Infographic showing various Junior Rtl Design Engineer job openings in Missouri as of August 2026, with employment types broken down into 87% Full Time, 8% Part Time, and 5% Contract. Highlights an 85% Physical, 4% Hybrid, and 11% Remote job distribution, with an average salary of $67,348 per year, or $32.4 per hour.

ASIC Engineering Technical Leader - CDC

Jobtailor

California, MO • On-site

$130 - $180/hr

Other

Posted 17 days ago

Job description

Responsibilities
  • Define, design and verify ASIC and ASIC subsystems to be deployed in a range of Cisco platforms
  • Contribute to a multi-disciplined engineering team to meet the power, performance, and area goals for products
  • Design, document, and develop ASIC subsystems for release in high volume and quality
  • Help define the process, methods, and tools for design and implementation of complex developments
  • Lead the CDC/RDC (Clock Domain Crossing / Reset Domain Crossing) methodology in silicon one chips
  • Design and implement robust and reusable RTL with CDC/RDC considerations
  • Spec comprehensive CDC/RDC check flows and work with CAD team to implement
  • Review and approve CDC/RDC constraints and waivers
  • Perform static glitch analysis
  • Improve design with prevention of static glitch hazard
Requirements
  • Bachelor’s with 8+ years or related experience, or master’s with 6 + years of related experience, or PhD + 3 years of related experience
  • Prior experience with RTL development skills and experiences
  • Prior experience with CDC/RDC concepts and relevant design implementation
  • Prior Experience on maintaining CDC/RDC flow and signing-off constraints and waivers
  • Prior experience with static glitch hazards and relevant analysis on synthesis optimized gate netlists
  • Experience on SDC constraints development (Preferred)
  • Experience on VCS simulation SVA (SystemVerilog Assertions) (Preferred)
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