SoC Design Engineer
$156K - $160K/yr
SoC Design Engineer Job Duties ... Be responsible for digital design of ASIC cores within image sensor SoC products, including IP ...
$156K - $160K/yr
SoC Design Engineer Job Duties ... Be responsible for digital design of ASIC cores within image sensor SoC products, including IP ...
$156K - $160K/yr
SoC Design Engineer Job Duties ... Be responsible for digital design of ASIC cores within image sensor SoC products, including IP ...
Austin, TX · Hybrid
$164K/yr
This is a great opportunity for a seasoned engineer to develop and implement a world-class IP-Design Management Platform in a fast-paced production environment on the cutting edge of modern ...
Austin, TX · Hybrid
$164K/yr
This is a great opportunity for a seasoned engineer to develop and implement a world-class IP-Design Management Platform in a fast-paced production environment on the cutting edge of modern ...
Cupertino, CA · On-site
$126.80 - $190.90/hr
Description As a Pixel IP DMA Design Engineer in the Pixel IP team, you will work closely with architecture, design, and verification teams to build high performance and low power DMA engines that ...
Cupertino, CA · On-site
$126.80 - $190.90/hr
Description As a Pixel IP DMA Design Engineer in the Pixel IP team, you will work closely with architecture, design, and verification teams to build high performance and low power DMA engines that ...
SoC Design Engineer Job Duties ... Be responsible for digital design of ASIC cores within image sensor SoC products, including IP ...
Quick apply
SoC Design Engineer Job Duties ... Be responsible for digital design of ASIC cores within image sensor SoC products, including IP ...
Santa Clara, CA · On-site
$156K - $160K/yr
SoC Design Engineer Job Duties ... Be responsible for digital design of ASIC cores within image sensor SoC products, including IP ...
Santa Clara, CA · On-site
$156K - $160K/yr
SoC Design Engineer Job Duties ... Be responsible for digital design of ASIC cores within image sensor SoC products, including IP ...
$102K - $139K/yr
The Engineer will work closely with the sales staff to provide both general and specific ... AV over IP design experience Education/Experience: * High school diploma or equivalent * A minimum ...
$102K - $139K/yr
The Engineer will work closely with the sales staff to provide both general and specific ... AV over IP design experience Education/Experience: * High school diploma or equivalent * A minimum ...
San Diego, CA · On-site
$106K - $145K/yr
... IP delivery for next-generation wireless ASIC platforms. The ideal candidate combines strong digital design verification skills with a solid understanding of modem PHY and DSP systems. This engineer ...
San Diego, CA · On-site
$106K - $145K/yr
... IP delivery for next-generation wireless ASIC platforms. The ideal candidate combines strong digital design verification skills with a solid understanding of modem PHY and DSP systems. This engineer ...
San Diego, CA · On-site
$269.17 - $376.84/hr
## Principal Modem PHY IP Design Verification Engineer - TerawaveApplylocations: Central Texas: Bay Area, CA: San Diego, CAtime type: Full timeposted on: Posted Todayjob requisition id:
San Diego, CA · On-site
$269.17 - $376.84/hr
## Principal Modem PHY IP Design Verification Engineer - TerawaveApplylocations: Central Texas: Bay Area, CA: San Diego, CAtime type: Full timeposted on: Posted Todayjob requisition id:
As a Senior ASIC Design Engineer, you will own the complete RTL design lifecycle from micro ... Integrate complex ASIC IP blocks into full-chip SOC environment, ensuring proper connectivity ...
As a Senior ASIC Design Engineer, you will own the complete RTL design lifecycle from micro ... Integrate complex ASIC IP blocks into full-chip SOC environment, ensuring proper connectivity ...
Bodega Bay, CA · On-site
$118K - $162K/yr
... IP delivery for next-generation wireless ASIC platforms. The ideal candidate combines strong digital design verification skills with a solid understanding of modem PHY and DSP systems. This engineer ...
Bodega Bay, CA · On-site
$118K - $162K/yr
... IP delivery for next-generation wireless ASIC platforms. The ideal candidate combines strong digital design verification skills with a solid understanding of modem PHY and DSP systems. This engineer ...
San Jose, CA · On-site
$145K/yr
As a Senior ASIC Design Engineer, you will own the complete RTL design lifecycle from micro ... Integrate complex ASIC IP blocks into full-chip SOC environment, ensuring proper connectivity ...
San Jose, CA · On-site
$145K/yr
As a Senior ASIC Design Engineer, you will own the complete RTL design lifecycle from micro ... Integrate complex ASIC IP blocks into full-chip SOC environment, ensuring proper connectivity ...
San Jose, CA · On-site
$149K - $215K/yr
About the Role Join Altera as a Senior FPGA Silicon Design Engineer focused on the design and ... Design and develop complex FPGA circuits and IP, including FPGA core fabric logic, interconnect and ...
San Jose, CA · On-site
$149K - $215K/yr
About the Role Join Altera as a Senior FPGA Silicon Design Engineer focused on the design and ... Design and develop complex FPGA circuits and IP, including FPGA core fabric logic, interconnect and ...
Job Title: 3D Stacked DRAM-on-Logic Design Engineer Office Location: San Jose, CA Job Type ... Provide digital IP services for 3D-stacked DRAM to enable DRAM-on-Logic system configurations for ...
Job Title: 3D Stacked DRAM-on-Logic Design Engineer Office Location: San Jose, CA Job Type ... Provide digital IP services for 3D-stacked DRAM to enable DRAM-on-Logic system configurations for ...
This dynamic role requires a versatile engineer who engages with IP design teams and internal/external customers across all phases of IP development - from architecture through post-silicon ...
This dynamic role requires a versatile engineer who engages with IP design teams and internal/external customers across all phases of IP development - from architecture through post-silicon ...
We are looking for a Sr. Design Engineer - IP Office to work in the dynamic Microsoft Artificial Intelligence Silicon Engineering team. Be a highly motivated self-starter with deep semiconductor IP ...
We are looking for a Sr. Design Engineer - IP Office to work in the dynamic Microsoft Artificial Intelligence Silicon Engineering team. Be a highly motivated self-starter with deep semiconductor IP ...
San Jose, CA · On-site
Drive OVM/UVM design verification and support FPGA engineers for early prototyping. * Execute RTL ... Support IP integration to SoC, including soft-IP RTL integration and hard-IP GDS macro integration.
Quick apply
San Jose, CA · On-site
Drive OVM/UVM design verification and support FPGA engineers for early prototyping. * Execute RTL ... Support IP integration to SoC, including soft-IP RTL integration and hard-IP GDS macro integration.
This dynamic role requires a versatile engineer who engages with IP design teams and internal/external customers across all phases of IP development - from architecture through post-silicon ...
This dynamic role requires a versatile engineer who engages with IP design teams and internal/external customers across all phases of IP development - from architecture through post-silicon ...
This dynamic role requires a versatile engineer who engages with IP design teams and internal/external customers across all phases of IP development - from architecture through post-silicon ...
This dynamic role requires a versatile engineer who engages with IP design teams and internal/external customers across all phases of IP development - from architecture through post-silicon ...
This dynamic role requires a versatile engineer who engages with IP design teams and internal/external customers across all phases of IP development - from architecture through post-silicon ...
This dynamic role requires a versatile engineer who engages with IP design teams and internal/external customers across all phases of IP development - from architecture through post-silicon ...
$175K - $311K/yr
... Mixed Signal IP Engineer! As a member of our dynamic group, you will have the rare and great ... LDO, ADC, DAC, PLL, Serdes, bandgap reference, filter design, switched capacitor circuit design ...
$175K - $311K/yr
... Mixed Signal IP Engineer! As a member of our dynamic group, you will have the rare and great ... LDO, ADC, DAC, PLL, Serdes, bandgap reference, filter design, switched capacitor circuit design ...
$40.5K - $51.2K
2% of jobs
$51.2K - $62K
11% of jobs
$67.7K is the 25th percentile. Wages below this are outliers.
$62K - $72.7K
23% of jobs
The median wage is $79.6K / yr.
$72.7K - $83.4K
22% of jobs
$83.4K - $94.1K
17% of jobs
$94.4K is the 75th percentile. Wages above this are outliers.
$94.1K - $104.9K
9% of jobs
$104.9K - $115.6K
6% of jobs
$115.6K - $126.3K
3% of jobs
$126.3K - $137K
3% of jobs
$137K - $147.8K
2% of jobs
$147.8K - $158.5K
1% of jobs
$40.5K
$88.2K
$158.5K
| Aspect | Ip Design Engineer | Network Engineer |
|---|---|---|
| Credentials | Bachelor's in Electrical Engineering, Computer Engineering, or related field; certifications like CCNP, CCIE | Bachelor's in Computer Science, Information Technology, or related; certifications like CCNA, CCNP |
| Work Environment | Designing IP networks, working in labs or office settings, focusing on network architecture | Managing, configuring, and troubleshooting networks in various environments |
| Industry Usage | Telecommunications, networking hardware companies, ISPs | IT departments, service providers, enterprise networks |
Ip Design Engineers focus on designing and planning IP network architectures, ensuring efficient data flow and scalability. Network Engineers implement, manage, and troubleshoot these networks in real-world environments. While both roles require networking certifications and technical expertise, the Ip Design Engineer emphasizes planning and design, whereas the Network Engineer concentrates on deployment and maintenance.
The top searched job categories for Ip Design Engineer jobs are:

$156K - $160K/yr
Full-time
Re-posted 15 days ago
Sourced by ZipRecruiter
Software development
1,001 - 5,000 Employees
Santa Clara, CA, US
1995