SoC Design Engineer
Santa Clara, CA Β· On-site
$156K - $160K/yr
SoC Design Engineer Job Duties ... Responsible for digital design and verification of image sensor and SoC systems, including IP ...
Santa Clara, CA Β· On-site
$156K - $160K/yr
SoC Design Engineer Job Duties ... Responsible for digital design and verification of image sensor and SoC systems, including IP ...
Santa Clara, CA Β· On-site
$156K - $160K/yr
SoC Design Engineer Job Duties ... Responsible for digital design and verification of image sensor and SoC systems, including IP ...
$269K - $376K/yr
This engineer will work closely with systems, ASIC, RF, verification, FPGA, firmware, and validation teams to deliver robust and efficient PHY IP. Responsibilities Design and develop modem PHY IP ...
$269K - $376K/yr
This engineer will work closely with systems, ASIC, RF, verification, FPGA, firmware, and validation teams to deliver robust and efficient PHY IP. Responsibilities Design and develop modem PHY IP ...
$269K - $376K/yr
This engineer will work closely with systems, ASIC, RF, verification, FPGA, firmware, and validation teams to deliver robust and efficient PHY IP. Responsibilities Design and develop modem PHY IP ...
$269K - $376K/yr
This engineer will work closely with systems, ASIC, RF, verification, FPGA, firmware, and validation teams to deliver robust and efficient PHY IP. Responsibilities Design and develop modem PHY IP ...
Santa Clara, CA Β· On-site
$156K - $160K/yr
SoC Design Engineer Job Duties ... Responsible for digital design and verification of image sensor and SoC systems, including IP ...
Santa Clara, CA Β· On-site
$156K - $160K/yr
SoC Design Engineer Job Duties ... Responsible for digital design and verification of image sensor and SoC systems, including IP ...
IP Network Design Engineer, Long-Term Design & Delivery Responsibilities: * Own long-term IP backbone design for one or more domains or regions -- translating business demand into topology, product ...
IP Network Design Engineer, Long-Term Design & Delivery Responsibilities: * Own long-term IP backbone design for one or more domains or regions -- translating business demand into topology, product ...
Santa Clarita, CA Β· On-site
$124K - $172K/yr
Semiconductor We are seeking a highly skilled Senior FPGA Design Engineer with 7 to 15 years of experience in RTL design, IP design and development, and FPGA validation and testing. The ideal ...
Quick apply
Santa Clarita, CA Β· On-site
$124K - $172K/yr
Semiconductor We are seeking a highly skilled Senior FPGA Design Engineer with 7 to 15 years of experience in RTL design, IP design and development, and FPGA validation and testing. The ideal ...
$156K - $160K/yr
SoC Design Engineer Job Duties ... Be responsible for digital design of ASIC cores within image sensor SoC products, including IP ...
$156K - $160K/yr
SoC Design Engineer Job Duties ... Be responsible for digital design of ASIC cores within image sensor SoC products, including IP ...
Santa Clara, CA Β· On-site
SoC Design Engineer Job Duties ... Be responsible for digital design of ASIC cores within image sensor SoC products, including IP ...
Quick apply
Santa Clara, CA Β· On-site
SoC Design Engineer Job Duties ... Be responsible for digital design of ASIC cores within image sensor SoC products, including IP ...
$156K - $160K/yr
SoC Design Engineer Job Duties ... Be responsible for digital design of ASIC cores within image sensor SoC products, including IP ...
$156K - $160K/yr
SoC Design Engineer Job Duties ... Be responsible for digital design of ASIC cores within image sensor SoC products, including IP ...
Santa Clara, CA Β· On-site
$156K - $160K/yr
SoC Design Engineer Job Duties ... Be responsible for digital design of ASIC cores within image sensor SoC products, including IP ...
Santa Clara, CA Β· On-site
$156K - $160K/yr
SoC Design Engineer Job Duties ... Be responsible for digital design of ASIC cores within image sensor SoC products, including IP ...
$102K - $139K/yr
The Engineer will work closely with the sales staff to provide both general and specific ... AV over IP design experience Education/Experience: * High school diploma or equivalent * A minimum ...
$102K - $139K/yr
The Engineer will work closely with the sales staff to provide both general and specific ... AV over IP design experience Education/Experience: * High school diploma or equivalent * A minimum ...
Sunnyvale, CA Β· On-site
$150K - $277K/yr
Description As a Pixel IP DMA Design Engineer in the Pixel IP team, you will work closely with architecture, design, and verification teams to build high performance and low power DMA engines that ...
Sunnyvale, CA Β· On-site
$150K - $277K/yr
Description As a Pixel IP DMA Design Engineer in the Pixel IP team, you will work closely with architecture, design, and verification teams to build high performance and low power DMA engines that ...
As a member of the front-end design/integration team, you will work closely with the architecture, IP design, Physical Design teams, and product engineers to achieve first pass silicon success. THE ...
As a member of the front-end design/integration team, you will work closely with the architecture, IP design, Physical Design teams, and product engineers to achieve first pass silicon success. THE ...
Eden Prairie, MN Β· On-site
$102K - $139K/yr
The Engineer will work closely with the sales staff to provide both general and specific ... AV over IP design experience Education/Experience: * High school diploma or equivalent * A minimum ...
Eden Prairie, MN Β· On-site
$102K - $139K/yr
The Engineer will work closely with the sales staff to provide both general and specific ... AV over IP design experience Education/Experience: * High school diploma or equivalent * A minimum ...
## Principal Modem PHY IP Design Verification Engineer - TerawaveApplylocations: Central Texas: Bay Area, CA: San Diego, CAtime type: Full timeposted on: Posted Todayjob requisition id:
## Principal Modem PHY IP Design Verification Engineer - TerawaveApplylocations: Central Texas: Bay Area, CA: San Diego, CAtime type: Full timeposted on: Posted Todayjob requisition id:
San Jose, CA Β· On-site
As a Senior ASIC Design Engineer, you will own the complete RTL design lifecycle from ... Integrate complex ASIC IP blocks into fullβchip SOC environment, ensuring proper connectivity ...
San Jose, CA Β· On-site
As a Senior ASIC Design Engineer, you will own the complete RTL design lifecycle from ... Integrate complex ASIC IP blocks into fullβchip SOC environment, ensuring proper connectivity ...
As a Senior ASIC Design Engineer, you will own the complete RTL design lifecycle from micro ... Integrate complex ASIC IP blocks into full-chip SOC environment, ensuring proper connectivity ...
As a Senior ASIC Design Engineer, you will own the complete RTL design lifecycle from micro ... Integrate complex ASIC IP blocks into full-chip SOC environment, ensuring proper connectivity ...
San Jose, CA Β· On-site
$145K/yr
As a Senior ASIC Design Engineer, you will own the complete RTL design lifecycle from micro ... Integrate complex ASIC IP blocks into full-chip SOC environment, ensuring proper connectivity ...
San Jose, CA Β· On-site
$145K/yr
As a Senior ASIC Design Engineer, you will own the complete RTL design lifecycle from micro ... Integrate complex ASIC IP blocks into full-chip SOC environment, ensuring proper connectivity ...
Bodega Bay, CA Β· On-site
$118K - $162K/yr
... IP delivery for next-generation wireless ASIC platforms. The ideal candidate combines strong digital design verification skills with a solid understanding of modem PHY and DSP systems. This engineer ...
Bodega Bay, CA Β· On-site
$118K - $162K/yr
... IP delivery for next-generation wireless ASIC platforms. The ideal candidate combines strong digital design verification skills with a solid understanding of modem PHY and DSP systems. This engineer ...
... IP delivery for next-generation wireless ASIC platforms. The ideal candidate combines strong digital design verification skills with a solid understanding of modem PHY and DSP systems. This engineer ...
... IP delivery for next-generation wireless ASIC platforms. The ideal candidate combines strong digital design verification skills with a solid understanding of modem PHY and DSP systems. This engineer ...
$40.5K - $51.2K
2% of jobs
$51.2K - $62K
11% of jobs
$67.7K is the 25th percentile. Wages below this are outliers.
$62K - $72.7K
23% of jobs
The median wage is $79.6K / yr.
$72.7K - $83.4K
22% of jobs
$83.4K - $94.1K
17% of jobs
$94.4K is the 75th percentile. Wages above this are outliers.
$94.1K - $104.9K
9% of jobs
$104.9K - $115.6K
6% of jobs
$115.6K - $126.3K
3% of jobs
$126.3K - $137K
3% of jobs
$137K - $147.8K
2% of jobs
$147.8K - $158.5K
1% of jobs
$40.5K
$88.2K
$158.5K
| Aspect | Ip Design Engineer | Network Engineer |
|---|---|---|
| Credentials | Bachelor's in Electrical Engineering, Computer Engineering, or related field; certifications like CCNP, CCIE | Bachelor's in Computer Science, Information Technology, or related; certifications like CCNA, CCNP |
| Work Environment | Designing IP networks, working in labs or office settings, focusing on network architecture | Managing, configuring, and troubleshooting networks in various environments |
| Industry Usage | Telecommunications, networking hardware companies, ISPs | IT departments, service providers, enterprise networks |
Ip Design Engineers focus on designing and planning IP network architectures, ensuring efficient data flow and scalability. Network Engineers implement, manage, and troubleshoot these networks in real-world environments. While both roles require networking certifications and technical expertise, the Ip Design Engineer emphasizes planning and design, whereas the Network Engineer concentrates on deployment and maintenance.
For Ip Design Engineer jobs, the most frequently searched job titles are:

Santa Clara, CA β’ On-site
$156K - $160K/yr
Full-time
Re-posted 7 days ago
Sourced by ZipRecruiter
Software development
1,001 - 5,000 Employees
Santa Clara, CA, US
1995