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Ip Design Engineer Jobs (NOW HIRING)

Apple

ASIC Design Engineer - Pixel IP

Sunnyvale, CA · On-site

$129K - $194K/yr

Description As an ASIC Design Engineer in the Pixel IP design team, you will work closely with architecture, design, and verification teams to build high performance and low power pixel processing ...

Apple

ASIC Design Engineer - Pixel IP

Sunnyvale, CA · On-site

$150K - $277K/yr

Description As an ASIC Design Engineer in the Pixel IP design team, you will work closely with architecture, design, and verification teams to design high performance and low power pixel processing ...

Apple

ASIC Design Engineer - Pixel IP

Sunnyvale, CA · On-site

$184K - $324K/yr

Description As an ASIC Design Engineer in the Pixel IP design team, you will work closely with architecture, design, and verification teams to design high performance and low power pixel processing ...

Apple Inc.

ASIC Design Engineer -- Pixel IP

Sunnyvale, CA · On-site

$129K - $194K/yr

Description As an ASIC Design Engineer in the Pixel IP design team, you will work closely with architecture, design, and verification teams to design high performance and low power pixel processing ...

NXP Semiconductors

IP Design Architect

Austin, TX

IP Design Architect Location: Austin, Texas Role Summary: * If you're passionate about IP ... Master's preferred in EE, Computer Engineering * 5+ years of experience in architecture, modeling ...

Infotech Sourcing

Design Engineer III

Austin, TX

Job Title: Core Engineering - Design Engineer III Duration: 12 months with possible extension ... Experience analyzing Intellectual Property (IP) design for power characteristics and building run ...

Infotech Sourcing

Design Engineer III

Austin, TX · On-site

Job Title: Core Engineering - Design Engineer III Duration: 12 months with possible extension ... Experience analyzing Intellectual Property (IP) design for power characteristics and building run ...

Apple

ASIC Design Engineer - Pixel IP DMA

Sunnyvale, CA · On-site

$184K - $324K/yr

Description As a Pixel IP DMA Design Engineer in the Pixel IP team, you will work closely with architecture, design, and verification teams to build high performance and low power DMA engines that ...

Apple

ASIC Design Engineer - Pixel IP DMA

Cupertino, CA · On-site

$150K - $277K/yr

Description As a Pixel IP DMA Design Engineer in the Pixel IP team, you will work closely with architecture, design, and verification teams to build high performance and low power DMA engines that ...

Apple

ASIC Design Engineer - Pixel IP DMA

Cupertino, CA

$150K - $277K/yr

Description As a Pixel IP DMA Design Engineer in the Pixel IP team, you will work closely with architecture, design, and verification teams to build high performance and low power DMA engines that ...

Apple

ASIC Design Engineer - Pixel IP DMA

Cupertino, CA · On-site

$129K - $194K/yr

Description As a Pixel IP DMA Design Engineer in the Pixel IP team, you will work closely with architecture, design, and verification teams to build high performance and low power DMA engines that ...

Apple

ASIC Design Engineer - Pixel IP DMA

Cupertino, CA

$129K - $194K/yr

Description As a Pixel IP DMA Design Engineer in the Pixel IP team, you will work closely with architecture, design, and verification teams to build high performance and low power DMA engines that ...

H R PUNDITS INC

Design Engineer III

Austin, TX · On-site

$120K/yr

Design Engineer III ONSITE- US: TX- Austin OR Sunnyvale office (2nd option) Salary 140 to 145K ... Experience analyzing Intellectual Property (IP) design for power characteristics and building run ...

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Ip Design Engineer information

See salary details

$40.5K

$88.2K

$158.5K

How much do ip design engineer jobs pay per year?

As of Sep 13, 2026, the average yearly pay for ip design engineer in the United States is $88,150.00, according to ZipRecruiter salary data. Most workers in this role earn between $68,000.00 and $98,500.00 per year, depending on experience, location, and employer.

What is an IP design engineer?

IP Design Engineers are specialized professionals who design, develop, and validate intellectual property (IP) cores used in semiconductor devices such as microprocessors, FPGAs, and ASICs. They create reusable hardware design blocks that can be integrated into larger systems-on-chip (SoCs), optimizing for performance, power, and area. Their work involves using hardware description languages like VHDL or Verilog, collaborating with verification teams, and ensuring compliance with industry standards. IP Design Engineers play a crucial role in enabling faster, more efficient chip development in the semiconductor industry.

What are the key skills and qualifications needed to thrive as an IP design engineer?

To thrive as an IP Design Engineer, you need a solid background in digital design, computer architecture, and hardware description languages (HDLs) like Verilog or VHDL, typically supported by a degree in electrical or computer engineering. Familiarity with EDA tools such as Synopsys, Cadence, or Mentor Graphics, as well as knowledge of verification methodologies and relevant industry certifications, is highly beneficial. Strong problem-solving skills, teamwork, and effective communication help you collaborate efficiently with cross-functional teams and resolve complex design challenges. These skills are crucial for delivering high-quality, reusable IP cores that meet performance, power, and area requirements in competitive semiconductor markets.

What are some typical challenges an IP design engineer may encounter when integrating third-party IP blocks into a larger system-on-chip (SoC) design?

One common challenge for IP Design Engineers is ensuring that third-party IP blocks are compatible with the overall architecture and meet performance, timing, and power requirements of the SoC. Integration often involves resolving interface mismatches, addressing protocol differences, and debugging functional issues during system verification. Close collaboration with verification engineers and other design teams is crucial to efficiently identify and resolve integration problems, ensuring a smooth handoff from design to manufacturing.

What is the difference between Ip Design Engineer vs Network Engineer?

AspectIp Design EngineerNetwork Engineer
CredentialsBachelor's in Electrical Engineering, Computer Engineering, or related field; certifications like CCNP, CCIEBachelor's in Computer Science, Information Technology, or related; certifications like CCNA, CCNP
Work EnvironmentDesigning IP networks, working in labs or office settings, focusing on network architectureManaging, configuring, and troubleshooting networks in various environments
Industry UsageTelecommunications, networking hardware companies, ISPsIT departments, service providers, enterprise networks

Ip Design Engineers focus on designing and planning IP network architectures, ensuring efficient data flow and scalability. Network Engineers implement, manage, and troubleshoot these networks in real-world environments. While both roles require networking certifications and technical expertise, the Ip Design Engineer emphasizes planning and design, whereas the Network Engineer concentrates on deployment and maintenance.

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For Ip Design Engineer jobs, the most frequently searched job titles are:

Ip Design Engineer jobs near you
Infographic showing various Ip Design Engineer job openings in the United States as of September 2026, with employment types broken down into 1% Internship, 87% Full Time, 9% Part Time, and 3% Contract. Highlights an 81% Physical, 4% Hybrid, and 15% Remote job distribution, with an average salary of $88,150 per year, or $42.4 per hour.

3D Stacked Logic Design Engineer

San Jose, CA

SK hynix America
Semiconductor and Electronic Component Manufacturing • 201 - 500 employees
Learn more about SK hynix Americaexternal

Full-time

Medical, Retirement, PTO

Re-posted 27 days ago

Job description

Job Title: 3D Stacked Logic Design Engineer
Office Location: San Jose, CA
Job Type: Full-Time
Work Model: Onsite 

Job Summary:

To strengthen leadership in the DRAM-on-Logic era through optimized DRAM die design, we are seeking talent capable of driving the co-design of 3D-stacked DRAM logic dies in close collaboration with U.S.-based customers. This strategic hiring initiative aims to enhance our global competitiveness by fostering deep engagement with key American clients, ensuring that our die design solutions are precisely aligned with their evolving technical requirements and market demands.

Responsibilities:

  • Strengthen leadership in the DRAM-on-Logic era through advanced digital IP design for 3D-stacked DRAM.
  • Provide digital IP services for 3D-stacked DRAM to enable DRAM-on-Logic system configurations for customers.
  • Co-design 3D-stacked DRAM Logic Dies with U.S.-based customers.
  • Improve competitiveness through close engagement with customers in the U.S.
  • Design high-speed digital IP for 3D-stacked DRAM peripheral circuits and DRAM DFT with U.S.-based customers, covering RTL design to implementation.
  • Conduct foundry verification of service-ready IPs and setting up infrastructure for the IP business.
  • Deliver services to ensure seamless IP integration in customer design environments.
  • Design digital logic blocks for 3D-stacked DRAM peripherals and Design-for-Test (DFT) features.
  • Establish close technical engagement with key U.S.-based customers to address immediate 3D-stacked DRAM requirements.
  • Establish close technical engagement with foundry partners (e.g., TSMC, Intel) to build digital IP for 3D-stacked DRAM.

Qualifications:   

  • Bachelor's degree or higher in Electrical Engineering or a related discipline with 5+ years of relevant experience.
  • Development of Digital Logic IP/SoC based on Hardware Description Languages (Verilog, VHDL).
  • Experience in RTL design and implementation memory PHY, hard macro IP for high-speed circuit, or high-speed digital IP design.
  • Experience with memory controllers.
  • Experience in memory Built-in Self-Test (BIST), DRAM Design for Test (DFT) / Design for Debug (DFD).
  • Deep understanding of PPA analysis and optimization, and physical design.
  • Excellent verbal and written communication in English; ability to present technical concepts to cross functional teams and senior management.

Benefits:

  • Top Tier health insurance at no employee cost
  • Paid day offs: Paid Time Off, Company Holidays, Parental Leave, Happy Fridays
  • 401k Matching
  • Flexible Spending Account (FSA) for Health Care & Dependent Care
  • Educational reimbursement up to $10,000 per year
  • Donation Matching and volunteering opportunities
  • Corporate discount programs
  • Free Breakfast/Lunch/Dinner provided to employees
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About SK Hynix America

Sourced by ZipRecruiter

Industry

Semiconductor and electronic component manufacturing

Company size

201 - 500 Employees

Headquarters location

San Jose, CA, US

Year founded

1983

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