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Ip Design Engineer Jobs (NOW HIRING)

Intel

IP Design Verification Engineer

Santa Clara, CA

$141K - $200K/yr

As an IP Verification Engineer, you will be working on UCIe Mixed-Signal IP delivering to multiple ... Closely working with design team to review specifications and architecture, define verification ...

Apple

ASIC Design Engineer - Pixel IP DMA

Cupertino, CA

$129K - $194K/yr

Description As a Pixel IP DMA Design Engineer in the Pixel IP team, you will work closely with architecture, design, and verification teams to build high performance and low power DMA engines that ...

Apple

ASIC Design Engineer - Pixel IP DMA

Cupertino, CA

$150K - $277K/yr

Description As a Pixel IP DMA Design Engineer in the Pixel IP team, you will work closely with architecture, design, and verification teams to build high performance and low power DMA engines that ...

Apple

ASIC Design Engineer - Pixel IP DMA

Cupertino, CA

$150K - $277K/yr

Description As a Pixel IP DMA Design Engineer in the Pixel IP team, you will work closely with architecture, design, and verification teams to build high performance and low power DMA engines that ...

NXP Semiconductors

IP Design Architect

Austin, TX

IP Design Architect Location: Austin, Texas Role Summary: * If you're passionate about IP ... Master's preferred in EE, Computer Engineering * 5+ years of experience in architecture, modeling ...

Apple

ASIC Design Engineer - Pixel IP DMA

Cupertino, CA

$129K - $194K/yr

Description As a Pixel IP DMA Design Engineer in the Pixel IP team, you will work closely with architecture, design, and verification teams to build high performance and low power DMA engines that ...

Apple

ASIC Design Engineer - Pixel IP DMA

Sunnyvale, CA

$184K - $324K/yr

Description As a Pixel IP DMA Design Engineer in the Pixel IP team, you will work closely with architecture, design, and verification teams to build high performance and low power DMA engines that ...

H R PUNDITS INC

Design Engineer III

Austin, TX · On-site

$120K/yr

Design Engineer III ONSITE- US: TX- Austin OR Sunnyvale office (2nd option) Salary 140 to 145K ... Experience analyzing Intellectual Property (IP) design for power characteristics and building run ...

Qualcomm

Digital Design Engineer

San Diego, CA · On-site

$115K - $173K/yr

Engineering Group, Engineering Group > ASICS Engineering General Summary: Qualcomm's high speed ... Expertise required on digital IP design using System Verilog, logic synthesis, linting checks ...

Intel

Analog IP Design Execution Manager

Phoenix, AZ · On-site

$200K/yr

The Hard IP and Test Chip Development team, within Intel's Central Engineering Group, is ... Drawing on prior design experience, identify technical problems and take the lead to drive ...

Intel

Analog IP Design Execution Manager

Hillsboro, OR

$220K/yr

The Hard IP and Test Chip Development team, within Intel's Central Engineering Group, is ... Drawing on prior design experience, identify technical problems and take the lead to drive ...

Intel

Analog IP Design Execution Manager

Santa Clara, CA · On-site

$237K/yr

The Hard IP and Test Chip Development team, within Intel's Central Engineering Group, is ... Drawing on prior design experience, identify technical problems and take the lead to drive ...

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All JobsIp Design Engineer Jobs

Ip Design Engineer information

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$40.5K

$88.2K

$158.5K

How much do ip design engineer jobs pay per year?

As of Jul 9, 2026, the average yearly pay for ip design engineer in the United States is $88,150.00, according to ZipRecruiter salary data. Most workers in this role earn between $68,000.00 and $98,500.00 per year, depending on experience, location, and employer.

What are the key skills and qualifications needed to thrive as an IP Design Engineer, and why are they important?

To thrive as an IP Design Engineer, you need a solid background in digital design, computer architecture, and hardware description languages (HDLs) like Verilog or VHDL, typically supported by a degree in electrical or computer engineering. Familiarity with EDA tools such as Synopsys, Cadence, or Mentor Graphics, as well as knowledge of verification methodologies and relevant industry certifications, is highly beneficial. Strong problem-solving skills, teamwork, and effective communication help you collaborate efficiently with cross-functional teams and resolve complex design challenges. These skills are crucial for delivering high-quality, reusable IP cores that meet performance, power, and area requirements in competitive semiconductor markets.

What is the difference between Ip Design Engineer vs Network Engineer?

AspectIp Design EngineerNetwork Engineer
CredentialsBachelor's in Electrical Engineering, Computer Engineering, or related field; certifications like CCNP, CCIEBachelor's in Computer Science, Information Technology, or related; certifications like CCNA, CCNP
Work EnvironmentDesigning IP networks, working in labs or office settings, focusing on network architectureManaging, configuring, and troubleshooting networks in various environments
Industry UsageTelecommunications, networking hardware companies, ISPsIT departments, service providers, enterprise networks

Ip Design Engineers focus on designing and planning IP network architectures, ensuring efficient data flow and scalability. Network Engineers implement, manage, and troubleshoot these networks in real-world environments. While both roles require networking certifications and technical expertise, the Ip Design Engineer emphasizes planning and design, whereas the Network Engineer concentrates on deployment and maintenance.

What are some typical challenges an IP Design Engineer may encounter when integrating third-party IP blocks into a larger system-on-chip (SoC) design?

One common challenge for IP Design Engineers is ensuring that third-party IP blocks are compatible with the overall architecture and meet performance, timing, and power requirements of the SoC. Integration often involves resolving interface mismatches, addressing protocol differences, and debugging functional issues during system verification. Close collaboration with verification engineers and other design teams is crucial to efficiently identify and resolve integration problems, ensuring a smooth handoff from design to manufacturing.

What are IP Design Engineers?

IP Design Engineers are specialized professionals who design, develop, and validate intellectual property (IP) cores used in semiconductor devices such as microprocessors, FPGAs, and ASICs. They create reusable hardware design blocks that can be integrated into larger systems-on-chip (SoCs), optimizing for performance, power, and area. Their work involves using hardware description languages like VHDL or Verilog, collaborating with verification teams, and ensuring compliance with industry standards. IP Design Engineers play a crucial role in enabling faster, more efficient chip development in the semiconductor industry.
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What job categories do people searching Ip Design Engineer jobs look for? The top searched job categories for Ip Design Engineer jobs are:
Ip Design Engineer jobs near you
Infographic showing various Ip Design Engineer job openings in the United States as of July 2026, with employment types broken down into 89% Full Time, 8% Part Time, and 3% Contract. Highlights an 87% Physical, 3% Hybrid, and 10% Remote job distribution, with an average salary of $88,150 per year, or $42.4 per hour.
IP Design Verification Engineer

IP Design Verification Engineer

Intel

Santa Clara, CA

$141K - $200K/yr

Full-time

Medical, Retirement, PTO

Re-posted 5 hours ago

Intel rating

8.7

Company rating: 8.7 out of 10

Based on 145 frontline employees who took The Breakroom Quiz

10th of 141 rated electronics manufacturers

Job description

Job Details:Job Description: 

The world is transforming - and so is Intel. Here at Intel, we believe the world needs technology that can enrich the lives of every person on earth. We work every single day to design and manufacture silicon products that empower people's lives.

Do you love to solve technical challenges? Do you enjoy working with cross functional teams to deliver solutions for products ? If so, come join us to do something wonderful.

As an IP Verification Engineer, you will be working on UCIe Mixed-Signal IP delivering to multiple Server SoCs.

A successful candidate will have proven experience demonstrating the following skills and behavioral traits:

  • Analytical and problem-solving skills
  • Verbal/written communication skills
  • Effective team player with continuous learning mindset
  • Willingness to balance multiple tasks
  • Willingness to work in a fast-paced environment and have as much fun and growth as possible in the process

The primary responsibilities for this role will include, but are not limited to:

  • Test bench development, directed/constrained random test generation in UVM
  • Closely working with design team to review specifications and architecture, define verification plan, coverage, and improve methodology
  • Run RTL and gate level functional verification, debug failures, and analyze coverage
  • Support mixed-signal verification using Verilog models of analog IP
Qualifications:

Minimum Qualifications:

Minimum qualifications are required to be initially considered for this position.

  • The candidate must have a Bachelor's degree in Electrical/Computer Engineering or Computer Science and 5+ years of experience -OR- Master's degree in Electrical/Computer Engineering or Computer Science and 3+ years of experience -OR- PhD in Electrical/Computer Engineering or Computer Science and 2+ years of experience
  • Relevant Work experience include:
    • IP or SoC verification experience using System Verilog/UVM
    • Reading and interpreting technical specs and Register Transfer Level (RTL) code for debug
    • Implementation of verification environments that include use of constrained-random stimulus
    • Code/Functional Coverage analysis
    • Writing System Verilog Assertions (SVA)

Preferred Qualifications:

Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

  • Mixed-Signal Verification
  • Experience with UCIe or PCIe or I/O
Job Type:Experienced HireShift:Shift 1 (United States of America)Primary Location: US, California, Santa ClaraAdditional Locations:US, Oregon, HillsboroBusiness group:The Central Engineering Group (CEG) is Intel's data-driven organization that builds scalable engineering solutions across three pillars: Product Enablement (IP, tools, and methodologies), Custom ASIC (leveraging existing IP for custom silicon), and Foundry Enablement (supporting top customers and validating technologies). The team focuses on customer-driven, end-to-end solutions with short development cycles to deliver measurable business impact across Intel's product and foundry businesses.Posting Statement:All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.Position of TrustN/ABenefits

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel.

Annual Salary Range for jobs which could be performed in the US: $141,910.00-200,340.00 USDThe range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.

*

ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.

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About Intel

Sourced by ZipRecruiter

Intel strives to make every facet of semiconductor manufacturing state-of-the-art -- from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support. Employees in the Technology and Manufacturing Group are part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moore's Law to bring smart, connected devices to every person on Earth

Industry

Manufacturing

Company size

10,000+ Employees

Headquarters location

Santa Clara, CA, US

Year founded

1968

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