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Internship Signal Foundation Jobs (NOW HIRING)

$90 - $120/hr

The Memory Systems Engineering team develops the digital and mixed-signal foundation that enables ... internships, research, or industry experience. * Solid understanding of SystemVerilog RTL ...

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How much do internship signal foundation jobs pay per hour?

As of Sep 6, 2026, the average hourly pay for internship signal foundation in the United States is $17.31, according to ZipRecruiter salary data. Most workers in this role earn between $14.42 and $19.23 per hour, depending on experience, location, and employer.

What is the difference between Internship Signal Foundation vs Signal Processing Intern?

AspectInternship Signal FoundationSignal Processing Intern
Required CredentialsTypically pursuing or completed a degree in computer science, electrical engineering, or related fieldsSimilar educational background, often with coursework in signal processing or related areas
Work EnvironmentResearch labs, tech companies, or nonprofit organizations focused on signal technologyResearch and development teams within tech firms or academic institutions
Employer & Industry UsageUsed by organizations involved in signal technology, communications, or data analysisCommonly used in industries like telecommunications, audio/video processing, and research institutions

The Internship Signal Foundation and Signal Processing Intern roles share similar educational requirements and work environments, often within tech or research organizations. The main difference lies in the focus: the Internship Signal Foundation may be more aligned with nonprofit or foundational research efforts, while Signal Processing Internships are typically industry-focused on practical applications of signal analysis and processing.

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Cities with the most Internship Signal Foundation job openings:

What are the most commonly searched types of Signal Foundation jobs?

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What states have the most Internship Signal Foundation jobs?

States with the most job openings for Internship Signal Foundation jobs include:

Infographic showing various Internship Signal Foundation job openings in the United States as of August 2026, with employment types broken down into 1% Internship, 1% As Needed, 79% Full Time, 14% Part Time, and 5% Contract. Highlights an 92% Physical, 2% Hybrid, and 6% Remote job distribution, with an average salary of $35,995 per year, or $17.3 per hour.

New College Grad - Mixed Signal Design Engineer, HBM Richardson, Texas, United States of America Pos

Micron Technology, Inc

Richardson, TX • On-site

$90 - $120/hr

Other

Medical, Dental, Vision, PTO

Posted 5 days ago


Micron Technology rating

8.6

Company rating: 8.6 out of 10

Based on 43 frontline employees who took The Breakroom Quiz

26th of 161 rated electronics manufacturers


Job description

New College Grad - Mixed Signal Design Engineer, HBM (Evergreen)

Our vision is to transform how the world uses information to enrich life for all.

Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever.

The Memory Systems Engineering team develops the digital and mixed-signal foundation that enables Micron's High Bandwidth Memory (HBM) products. The team works across architecture, PHY, design verification, DFT, and silicon validation functions to deliver innovative memory solutions that achieve demanding performance, power, and reliability targets.

In this role, you'll receive mentorship from expert engineers while building expertise in sophisticated memory technologies. You will also contribute to the definition, implementation, integration, and validation of HBM base-die digital subsystems. You will collaborate with cross-disciplinary engineering groups to develop robust RTL solutions, support verification activities, and help ensure successful first-pass silicon execution. This position provides an opportunity to gain broad exposure to memory system design, silicon development methodologies, and AI-enabled engineering workflows.

Responsibilities
  • Define and implement digital micro-architecture for HBM base-die subsystems, including channel support logic, boot and initialization sequencing, training orchestration, configuration and status registers, telemetry, performance monitoring, and reliability features.
  • Translate system requirements into timing, power, and area objectives while partnering with physical layer and system architects; develop and maintain interface specifications for bus protocols, clock-domain crossings, and reset architectures.
  • Develop, integrate, and debug synthesizable SystemVerilog RTL, including multi-channel logic, interrupt handling, register maps, scan infrastructure, and design-for-test interfaces while supporting integration and ECO activities.
  • Work alongside design verification teams to build verification strategies, reach coverage goals, perform CDC/RDC analysis, and resolve RTL, testbench, and gate-level issues.
  • Support silicon bring-up and post-silicon validation through debug enablement, root-cause analysis, and partnership with DFT and test engineering teams; leverage AI-Assisted and AI-Enabled tools to improve engineering productivity, debug efficiency, and data-driven analysis.
Minimum Qualifications
  • Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field.
  • Experience with digital design, SoC integration, or semiconductor development through academic projects, internships, research, or industry experience.
  • Solid understanding of SystemVerilog RTL development, clock and reset architectures, CDC/RDC methodologies, and low-power design concepts.
  • Understanding of design-for-debug and design-for-test principles and the ability to collaborate effectively within multi-functional engineering teams.
  • Experience working in AI-Assisted or AI-Enabled environments, or demonstrated willingness to apply AI tools to support engineering workflows, debug activities, and technical analysis.
Preferred Qualifications
  • Exposure to post-silicon validation, silicon bring-up, or structured hardware debug methodologies.
  • Familiarity with scan, MBIST, LBIST, or related test and debug architectures.
  • Experience contributing to verification planning and partnering with design verification teams to achieve functional and code coverage objectives.
  • Knowledge of micro-architecture optimization, timing closure concepts, and design tradeoffs related to constraints and path intent.
  • Experience Applying AI, Employing AI, or Using AI for data analysis, debug automation, productivity enhancement, or performance optimization within semiconductor design environments.
Job Profile(s)
  • Systems Design Engineer 1 - Systems Design Engineer 2

Relocation Level: TBD

Micron benefits are designed to help you stay well, provide peace of mind and help you prepare for the future. We offer a choice of medical, dental and vision plans in all locations enabling team members to select the plans that best meet their family healthcare needs and budget. Micron also provides benefit programs that help protect your income if you are unable to work due to illness or injury, and paid family leave. Additionally, Micron benefits include a robust paid time-off program and paid holidays. For additional information regarding the Benefit programs available, please see the Benefits Guide posted on Benefits | Micron Technology, Inc

Micron is proud to be an equal opportunity workplace and is an affirmative action employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, age, national origin, citizenship status, disability, protected veteran status, gender identity or any other factor protected by applicable federal, state, or local laws.

For US Sites Only: To request assistance with the application process and/or for reasonable accommodations, please contact Micron’s People Organization at hrsupport_na@micron.com or 1-800-336-8918 (select option #3)

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