PHY RTL Design Engineer
$120K - $210K/yr
With a particular emphasis on highly energy-efficient design and new technologies that transform ... Power and Area efficient RTL logic design, and DV support. Running tools to ensure lint and CDC/RDC ...
PHY RTL Design Engineer
$120K - $210K/yr
With a particular emphasis on highly energy-efficient design and new technologies that transform ... Power and Area efficient RTL logic design, and DV support. Running tools to ensure lint and CDC/RDC ...
PHY RTL Design Engineer
$171K - $302K/yr
With a particular emphasis on highly energy-efficient design and new technologies that transform ... Power and Area efficient RTL logic design, and DV support. Running tools to ensure lint and CDC/RDC ...
PHY RTL Design Engineer
$171K - $302K/yr
With a particular emphasis on highly energy-efficient design and new technologies that transform ... Power and Area efficient RTL logic design, and DV support. Running tools to ensure lint and CDC/RDC ...
PHY RTL Design Engineer
$171K - $302K/yr
With a particular emphasis on highly energy-efficient design and new technologies that transform ... Power and Area efficient RTL logic design, and DV support. Running tools to ensure lint and CDC/RDC ...
PHY RTL Design Engineer
$171K - $302K/yr
With a particular emphasis on highly energy-efficient design and new technologies that transform ... Power and Area efficient RTL logic design, and DV support. Running tools to ensure lint and CDC/RDC ...
PHY RTL Design Engineer
$120K - $210K/yr
With a particular emphasis on highly energy-efficient design and new technologies that transform ... Power and Area efficient RTL logic design, and DV support. Running tools to ensure lint and CDC/RDC ...
PHY RTL Design Engineer
$120K - $210K/yr
With a particular emphasis on highly energy-efficient design and new technologies that transform ... Power and Area efficient RTL logic design, and DV support. Running tools to ensure lint and CDC/RDC ...
PHY RTL Design Engineer
$171K - $302K/yr
With a particular emphasis on highly energy-efficient design and new technologies that transform ... Power and Area efficient RTL logic design, and DV support. Running tools to ensure lint and CDC/RDC ...
PHY RTL Design Engineer
$171K - $302K/yr
With a particular emphasis on highly energy-efficient design and new technologies that transform ... Power and Area efficient RTL logic design, and DV support. Running tools to ensure lint and CDC/RDC ...
PHY RTL Design Engineer
$120K - $210K/yr
With a particular emphasis on highly energy-efficient design and new technologies that transform ... Power and Area efficient RTL logic design, and DV support. Running tools to ensure lint and CDC/RDC ...
PHY RTL Design Engineer
$120K - $210K/yr
With a particular emphasis on highly energy-efficient design and new technologies that transform ... Power and Area efficient RTL logic design, and DV support. Running tools to ensure lint and CDC/RDC ...
PHY RTL Design Engineer
$120K - $210K/yr
With a particular emphasis on highly energy-efficient design and new technologies that transform ... Power and Area efficient RTL logic design, and DV support. Running tools to ensure lint and CDC/RDC ...
PHY RTL Design Engineer
$120K - $210K/yr
With a particular emphasis on highly energy-efficient design and new technologies that transform ... Power and Area efficient RTL logic design, and DV support. Running tools to ensure lint and CDC/RDC ...
Debug SoC Design Engineer
$171K - $302K/yr
... transform the user experience at the product level. All of this is driven by a world-class ... Performance/power correlation - assist performance/power teams to diagnose suspected bottlenecks or ...
Debug SoC Design Engineer
$171K - $302K/yr
... transform the user experience at the product level. All of this is driven by a world-class ... Performance/power correlation - assist performance/power teams to diagnose suspected bottlenecks or ...
Debug SoC Design Engineer
$171K - $302K/yr
... transform the user experience at the product level. All of this is driven by a world-class ... Performance/power correlation - assist performance/power teams to diagnose suspected bottlenecks or ...
Debug SoC Design Engineer
$171K - $302K/yr
... transform the user experience at the product level. All of this is driven by a world-class ... Performance/power correlation - assist performance/power teams to diagnose suspected bottlenecks or ...
Debug SoC Design Engineer
$120K - $210K/yr
... transform the user experience at the product level. All of this is driven by a world-class ... Performance/power correlation - assist performance/power teams to diagnose suspected bottlenecks or ...
Debug SoC Design Engineer
$120K - $210K/yr
... transform the user experience at the product level. All of this is driven by a world-class ... Performance/power correlation - assist performance/power teams to diagnose suspected bottlenecks or ...
Debug SoC Design Engineer
$171K - $302K/yr
... transform the user experience at the product level. All of this is driven by a world-class ... Performance/power correlation - assist performance/power teams to diagnose suspected bottlenecks or ...
Debug SoC Design Engineer
$171K - $302K/yr
... transform the user experience at the product level. All of this is driven by a world-class ... Performance/power correlation - assist performance/power teams to diagnose suspected bottlenecks or ...
Debug SoC Design Engineer
$171K - $302K/yr
... transform the user experience at the product level. All of this is driven by a world-class ... Performance/power correlation - assist performance/power teams to diagnose suspected bottlenecks or ...
Debug SoC Design Engineer
$171K - $302K/yr
... transform the user experience at the product level. All of this is driven by a world-class ... Performance/power correlation - assist performance/power teams to diagnose suspected bottlenecks or ...
Debug SoC Design Engineer
$120K - $210K/yr
... transform the user experience at the product level. All of this is driven by a world-class ... Performance/power correlation - assist performance/power teams to diagnose suspected bottlenecks or ...
Debug SoC Design Engineer
$120K - $210K/yr
... transform the user experience at the product level. All of this is driven by a world-class ... Performance/power correlation - assist performance/power teams to diagnose suspected bottlenecks or ...
Debug SoC Design Engineer
$120K - $210K/yr
... transform the user experience at the product level. All of this is driven by a world-class ... Performance/power correlation - assist performance/power teams to diagnose suspected bottlenecks or ...
Debug SoC Design Engineer
$120K - $210K/yr
... transform the user experience at the product level. All of this is driven by a world-class ... Performance/power correlation - assist performance/power teams to diagnose suspected bottlenecks or ...
Debug SoC Design Engineer
$120K - $210K/yr
... transform the user experience at the product level. All of this is driven by a world-class ... Performance/power correlation - assist performance/power teams to diagnose suspected bottlenecks or ...
Debug SoC Design Engineer
$120K - $210K/yr
... transform the user experience at the product level. All of this is driven by a world-class ... Performance/power correlation - assist performance/power teams to diagnose suspected bottlenecks or ...
Debug SoC Design Engineer
$120K - $210K/yr
... transform the user experience at the product level. All of this is driven by a world-class ... Performance/power correlation - assist performance/power teams to diagnose suspected bottlenecks or ...
Debug SoC Design Engineer
$120K - $210K/yr
... transform the user experience at the product level. All of this is driven by a world-class ... Performance/power correlation - assist performance/power teams to diagnose suspected bottlenecks or ...
Debug SoC Design Engineer
$120K - $210K/yr
... transform the user experience at the product level. All of this is driven by a world-class ... Performance/power correlation - assist performance/power teams to diagnose suspected bottlenecks or ...
Debug SoC Design Engineer
$120K - $210K/yr
... transform the user experience at the product level. All of this is driven by a world-class ... Performance/power correlation - assist performance/power teams to diagnose suspected bottlenecks or ...
Design Engineer
Irvine, CA · On-site
Whether it's harnessing fusion through the science of stars, making exponential leaps in power ... We are not afraid to envision a future where fusion and science can transform our world. What you ...
Design Engineer
Irvine, CA · On-site
Whether it's harnessing fusion through the science of stars, making exponential leaps in power ... We are not afraid to envision a future where fusion and science can transform our world. What you ...
RFIC Design Engineer
$171K - $302K/yr
You'll work across fields to transform improved hardware elements into a coordinated design. Join ... Drive radio KPI (power, area, performance) to meet product requirements. Work with multi-functional ...
RFIC Design Engineer
$171K - $302K/yr
You'll work across fields to transform improved hardware elements into a coordinated design. Join ... Drive radio KPI (power, area, performance) to meet product requirements. Work with multi-functional ...
RFIC Design Engineer
$171K - $302K/yr
You'll work across fields to transform improved hardware elements into a coordinated design. Join ... Drive radio KPI (power, area, performance) to meet product requirements. Work with multi-functional ...
RFIC Design Engineer
$171K - $302K/yr
You'll work across fields to transform improved hardware elements into a coordinated design. Join ... Drive radio KPI (power, area, performance) to meet product requirements. Work with multi-functional ...
Internship Power Transformer Design information
See Riverside, CA salary details
$9.53 - $12.15
9% of jobs
$12.15 - $14.77
8% of jobs
$15.45 is the 25th percentile. Wages below this are outliers.
$14.77 - $17.40
28% of jobs
The median wage is $18.09 / hr.
$17.40 - $20.02
16% of jobs
$21.81 is the 75th percentile. Wages above this are outliers.
$20.02 - $22.64
20% of jobs
$22.64 - $25.26
9% of jobs
$25.26 - $27.88
4% of jobs
$27.88 - $30.50
1% of jobs
$30.50 - $33.13
1% of jobs
$33.13 - $35.75
1% of jobs
$35.75 - $38.37
2% of jobs
$9
$20
$38
How much do internship power transformer design jobs pay per hour?
As of Jun 9, 2026, the average hourly pay for internship power transformer design in Riverside, CA is $20.22, according to ZipRecruiter salary data. Most workers in this role earn between $15.05 and $22.55 per hour, depending on experience, location, and employer.
What is the difference between Internship Power Transformer Design vs Power Transformer Design Engineer?
| Aspect | Internship Power Transformer Design | Power Transformer Design Engineer |
|---|---|---|
| Credentials | Enrolled in electrical engineering or related program | Bachelor's or master's in electrical engineering, professional certifications |
| Work Environment | Internship setting, supervised, educational focus | Full-time engineering office or manufacturing plant |
| Industry Usage | Entry-level, training phase | Design, development, and testing of power transformers |
Internship Power Transformer Design roles are entry-level positions aimed at students gaining practical experience, while Power Transformer Design Engineers are fully qualified professionals responsible for designing and developing transformers. Internships provide foundational exposure, whereas engineers lead projects and make technical decisions.
What are popular job titles related to Internship Power Transformer Design jobs in Riverside, CA? For Internship Power Transformer Design jobs in Riverside, CA, the most frequently searched job titles are:
What job categories do people searching Internship Power Transformer Design jobs in Riverside, CA look for? The top searched job categories for Internship Power Transformer Design jobs in Riverside, CA are:
What cities near Riverside, CA are hiring for Internship Power Transformer Design jobs? Cities near Riverside, CA with the most Internship Power Transformer Design job openings:
$120K - $210K/yr
Full-time
Medical, Dental, Retirement
Posted 11 days ago
Apple rating
8.1
Based on 661 frontline employees who took The Breakroom Quiz
6th of 30 rated technology retailers
Job description
Come join Apple’s growing wireless silicon development team. Our wireless SOC organization is responsible for all aspects of wireless silicon development. With a particular emphasis on highly energy-efficient design and new technologies that transform the user experience at the product level, all of which is driven by a world-class vertically integrated engineering team spanning RF/Analog architecture, and design, Systems/PHY/MAC architecture and design, VLSI/RTL design and integration, Emulation, Design Verification, Test and Validation, and FW/SW engineering.
Description
Develop signal processing intensive design for wireless communication SoCs, including:
Writing specifications, other documents, and defining Microarchitecture based on MATLAB/C system model. Architecting area and power. Efficient low latency designs with scalabilities and flexibilities. Work with algorithm and software team to ensure performance and power efficiency. Power and Area efficient RTL logic design, and DV support. Running tools to ensure lint and CDC/RDC clean design. Synthesis and timing constraints. Experience in design of signal processing Wireless protocols.","responsibilities":"RTL coding and verification for PHY modem development.
Support banckend activities by reviewing the reports and appropriate adjustment of the design.
Involve in the pre and post silicon bringup process.
Preferred Qualifications
Familiarity with UVM DV environment and AI based efficiency improvement flows.
Strong fixed-point knowledge and extensive experience with bit-true cycle-accurate verifications.
Understanding of Decoders - Viterbi, LDPC, Polar.
Understanding of Filter design, multi-radix implementation, and compromises.
Knowledgeable in modern design techniques and energy-efficient/low power logic design, and power analysis.
Familiarity with power estimation (vector-less and vector-based), modeling, profiling, and post-silicon power correlation.
Solid understanding of wireless standards, such as IEEE 802.11, 802.15, Bluetooth or 3GPP is a plus.
Background in computer architecture.
Bus fabric, especially APB/AHB/AXI.
Power management with multiple power domains.
Ability to work well in a team and be productive under ambitious schedules.
Should exhibit excellent interpersonal skills and be self-motivated and well-organized.
Experience with FPGA and/or emulation platform desired.
Excellent communication skills - both written, and oral.
Minimum Qualifications
Bachelors degree in related field.
Understanding of DSP fundamentals.
Digital Communications knowledge.
Proficiency in RTL Design.
Pay & Benefits
At Apple, base pay is one part of our total compensation package and is determined within a range. This provides the opportunity to progress as you grow and develop within a role. The base pay range for this role is between $120,300 and $210,100, and your base pay will depend on your skills, qualifications, experience, and location.
Apple employees also have the opportunity to become an Apple shareholder through participation in Apple's discretionary employee stock programs. Apple employees are eligible for discretionary restricted stock unit awards, and can purchase Apple stock at a discount if voluntarily participating in Apple's Employee Stock Purchase Plan. You'll also receive benefits including: Comprehensive medical and dental coverage, retirement benefits, a range of discounted products and free services, and for formal education related to advancing your career at Apple, reimbursement for certain educational expenses - including tuition. Additionally, this role might be eligible for discretionary bonuses or commission payments as well as relocation. Learn more about Apple Benefits
Note: Apple benefit, compensation and employee stock programs are subject to eligibility requirements and other terms of the applicable plan or program.
Description
Develop signal processing intensive design for wireless communication SoCs, including:
Writing specifications, other documents, and defining Microarchitecture based on MATLAB/C system model. Architecting area and power. Efficient low latency designs with scalabilities and flexibilities. Work with algorithm and software team to ensure performance and power efficiency. Power and Area efficient RTL logic design, and DV support. Running tools to ensure lint and CDC/RDC clean design. Synthesis and timing constraints. Experience in design of signal processing Wireless protocols.","responsibilities":"RTL coding and verification for PHY modem development.
Support banckend activities by reviewing the reports and appropriate adjustment of the design.
Involve in the pre and post silicon bringup process.
Preferred Qualifications
Familiarity with UVM DV environment and AI based efficiency improvement flows.
Strong fixed-point knowledge and extensive experience with bit-true cycle-accurate verifications.
Understanding of Decoders - Viterbi, LDPC, Polar.
Understanding of Filter design, multi-radix implementation, and compromises.
Knowledgeable in modern design techniques and energy-efficient/low power logic design, and power analysis.
Familiarity with power estimation (vector-less and vector-based), modeling, profiling, and post-silicon power correlation.
Solid understanding of wireless standards, such as IEEE 802.11, 802.15, Bluetooth or 3GPP is a plus.
Background in computer architecture.
Bus fabric, especially APB/AHB/AXI.
Power management with multiple power domains.
Ability to work well in a team and be productive under ambitious schedules.
Should exhibit excellent interpersonal skills and be self-motivated and well-organized.
Experience with FPGA and/or emulation platform desired.
Excellent communication skills - both written, and oral.
Minimum Qualifications
Bachelors degree in related field.
Understanding of DSP fundamentals.
Digital Communications knowledge.
Proficiency in RTL Design.
Pay & Benefits
At Apple, base pay is one part of our total compensation package and is determined within a range. This provides the opportunity to progress as you grow and develop within a role. The base pay range for this role is between $120,300 and $210,100, and your base pay will depend on your skills, qualifications, experience, and location.
Apple employees also have the opportunity to become an Apple shareholder through participation in Apple's discretionary employee stock programs. Apple employees are eligible for discretionary restricted stock unit awards, and can purchase Apple stock at a discount if voluntarily participating in Apple's Employee Stock Purchase Plan. You'll also receive benefits including: Comprehensive medical and dental coverage, retirement benefits, a range of discounted products and free services, and for formal education related to advancing your career at Apple, reimbursement for certain educational expenses - including tuition. Additionally, this role might be eligible for discretionary bonuses or commission payments as well as relocation. Learn more about Apple Benefits
Note: Apple benefit, compensation and employee stock programs are subject to eligibility requirements and other terms of the applicable plan or program.
About Apple
Sourced by ZipRecruiter
Imagine what you could do here! At Apple, new ideas have a way of becoming extraordinary products, services, and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could accomplish. Dynamic, intelligent people and inspiring, innovative technologies are the norm here. The people who work here have reinvented entire industries with all Apple Hardware products. The same real passion for innovation that goes into our products also applies to our practices strengthening our dedication to leave the world better than we found it.
Industry
Computer and electronic product manufacturing
Company size
10,000+ Employees
Headquarters location
Cupertino, CA, US
Year founded
1976