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Internship Power Transformer Design Jobs in California

Our first product (Sohu) only supports transformers, but has an order of magnitude more throughput ... Work closely with Architects, Performance Engineers, Software Engineers, ASIC Design Engineers, and ...

Our first product (Sohu) only supports transformers, but has an order of magnitude more throughput ... Work closely with Architects, Performance Engineers, Software Engineers, ASIC Design Engineers, and ...

Our first product (Sohu) only supports transformers, but has an order of magnitude more throughput ... Work closely with Architects, Performance Engineers, Software Engineers, ASIC Design Engineers, and ...

Fall 2026 Internship - Graphic Design

Los Angeles, CA · On-site +1

$16.25 - $21.50/hr

Shaped by our belief in the unifying power of sports, music and entertainment, THETEAM leads with ... design or a related field * Must be able to earn college credit, as this is an unpaid internship

Electrical Engineer

Stockton, CA · On-site

$105K - $115K/yr

Design and develop high-frequency transformers and power RF filters. Create and optimize PCB designs for power electronics applications. Develop and test power electronics circuitry. Collaborate with ...

Showing results 41-60

Internship Power Transformer Design information

What is the difference between Internship Power Transformer Design vs Power Transformer Design Engineer?

AspectInternship Power Transformer DesignPower Transformer Design Engineer
CredentialsEnrolled in electrical engineering or related programBachelor's or master's in electrical engineering, professional certifications
Work EnvironmentInternship setting, supervised, educational focusFull-time engineering office or manufacturing plant
Industry UsageEntry-level, training phaseDesign, development, and testing of power transformers

Internship Power Transformer Design roles are entry-level positions aimed at students gaining practical experience, while Power Transformer Design Engineers are fully qualified professionals responsible for designing and developing transformers. Internships provide foundational exposure, whereas engineers lead projects and make technical decisions.

Does Internship Power Transformer Design do paid internships?

Internship programs for Power Transformer Design roles are often paid, especially in engineering companies that value attracting skilled students. Compensation varies by employer and location, and some internships may also offer stipends or academic credit. It is advisable to check specific company postings for detailed information on pay and benefits.

What are popular job titles related to Internship Power Transformer Design jobs in California?

For Internship Power Transformer Design jobs in California, the most frequently searched job titles are:

What job categories do people searching Internship Power Transformer Design jobs in California look for?

The top searched job categories for Internship Power Transformer Design jobs in California are:

What cities in California are hiring for Internship Power Transformer Design jobs?

Cities in California with the most Internship Power Transformer Design job openings:

Infographic showing various Internship Power Transformer Design job openings in California as of August 2026, with employment types broken down into 1% Internship, 76% Full Time, 17% Part Time, 2% Temporary, and 4% Contract. Highlights an 85% Physical, 4% Hybrid, and 11% Remote job distribution.

Power Optimization Engineer

Etched

Cupertino, CA

$2.0K/mo

Full-time

Medical, Dental, Vision

Re-posted 15 days ago


Job description

About Etched

Etched is building AI chips that are hard-coded for individual model architectures. Our first product (Sohu) only supports transformers, but has an order of magnitude more throughput and lower latency than a B200. With Etched ASICs, you can build products that would be impossible with GPUs, like real-time video generation models and extremely deep & parallel chain-of-thought reasoning agents.

Key responsibilities

  • Develop chip power model from chip architecture, estimate chip power from microarchitecture, and devise power saving techniques for product use cases.
  • Work closely with Architects, Performance Engineers, Software Engineers, ASIC Design Engineers, and Physical Design teams to implement design for optimal power using advanced power management techniques.
  • Estiate and analyze power consumption data at both full-chip and unit levels, guiding ASIC teams to enhance the power efficiency of all functional units both pre-silicon and post silicon. Correlate the estimated power consumption to the measured power.

You may be a good fit if you have

  • Experience in power optimization using dynamic voltage and frequency scaling techniques, power aware synthesis, glitch power reduction techniques as well as efficient power delivery network implementation.
  • Experience with gate-level power optimization through VCD-based and/or FSDB-based power analysis.
  • Strong understanding of concepts of energy consumption, estimation, data movement, low power design, and power-saving features.

Strong candidates may also have experience with

  • Digital design and optimization using industry-standard power analysis tools and methodologies.
  • Leading power optimization at RTL and layout level using PrimePower, VCD-based analysis, DVFS, clock power reduction, clock gating, and glitch reduction techniques.

Benefits

  • Full medical, dental, and vision packages, with 100% of premium covered
  • Housing subsidy of $2,000/month for those living within walking distance of the office
  • Daily lunch and dinner in our office
  • Relocation support for those moving to Cupertino

How we're different

Etched believes in the Bitter Lesson. We think most of the progress in the AI field has come from using more FLOPs to train and run models, and the best way to get more FLOPs is to build model-specific hardware. Larger and larger training runs encourage companies to consolidate around fewer model architectures, which creates a market for single-model ASICs.

We are a fully in-person team in Cupertino, and greatly value engineering skills. We do not have boundaries between engineering and research, and we expect all of our technical staff to contribute to both as needed.