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Internship Parametric Design Jobs in California (NOW HIRING)

Intel

Memory Circuit Design Engineer

Santa Clara, CA · On-site

Pre-Si verification, post-Si validation and debugging to enable yield and parametric tracking/ramp ... PhD with 1-2 years of professional experience gained through either internships or full-time ...

SpaceX

PCB Designer (Starship)

Hawthorne, CA · On-site

$100K - $120K/yr

... parametric data in CAD tools like Altium and Xpedition * Drive the future roadmap for SpaceX to ... internships and club/project work applies) PREFERRED SKILLS AND EXPERIENCE: * 2+ years of ...

SpaceX

PCB Designer (Starship)

Hawthorne, CA

$115K - $135K/yr

... parametric data in CAD tools like Altium and Xpedition * Drive the future roadmap for SpaceX to ... internships and club/project work applies) PREFERRED SKILLS AND EXPERIENCE: * 2+ years of ...

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Internship Parametric Design information

What is the difference between Internship Parametric Design vs Junior Parametric Designer?

AspectInternship Parametric DesignJunior Parametric Designer
CredentialsEnrolled in or recent graduate of relevant design/architecture programBachelor's degree in architecture, design, or related field
Work EnvironmentInternship setting, often in architecture or design firmsEntry-level professional role in design teams
ResponsibilitiesAssisting with parametric modeling, learning software toolsCreating parametric models, supporting project development

Internship Parametric Design positions are typically temporary roles for students or recent graduates gaining experience, while Junior Parametric Designers are entry-level professionals actively contributing to projects. Interns focus on learning and assisting, whereas Junior Designers take on more responsibility in project execution.

What is an internship in parametric design?

An internship in parametric design is a temporary position, often for students or recent graduates, that provides hands-on experience working with computational design tools and methodologies. Interns learn how to use software like Grasshopper or Rhino to create and manipulate complex design forms based on algorithms and data-driven parameters. The role typically involves assisting in the creation of digital models, exploring innovative architectural or engineering solutions, and collaborating with design teams. This internship helps build practical skills for a career in architecture, engineering, or related fields.

What types of projects and software tools can I expect to work with during an internship in parametric design?

As an intern in Parametric Design, you’ll typically work on projects involving architectural modeling, product design, or engineering solutions that leverage computational design techniques. You’ll likely use software such as Rhino with Grasshopper, Autodesk Revit with Dynamo, or other visual programming tools to create and optimize digital models. Expect to collaborate closely with architects, engineers, and other designers, contributing to iterative processes and learning how parametric methods are applied in real-world industry workflows. This hands-on experience will help you develop both technical and teamwork skills, which are highly valued in the field.

What are the key skills and qualifications needed to thrive as an internship in parametric design?

To thrive as an intern in parametric design, you need a solid grasp of architectural or engineering principles, along with experience in computational design and a relevant academic background. Familiarity with parametric modeling tools such as Grasshopper for Rhino, Autodesk Revit, and scripting languages like Python is typically required. Strong problem-solving skills, creativity, and effective communication help interns contribute innovative ideas and collaborate with multidisciplinary teams. These skills ensure you can efficiently develop, analyze, and communicate complex design solutions in dynamic project environments.
What are the most commonly searched types of Parametric Design jobs in California? The most popular types of Parametric Design jobs in California are:
What are popular job titles related to Internship Parametric Design jobs in California? For Internship Parametric Design jobs in California, the most frequently searched job titles are:
What job categories do people searching Internship Parametric Design jobs in California look for? The top searched job categories for Internship Parametric Design jobs in California are:
What cities in California are hiring for Internship Parametric Design jobs? Cities in California with the most Internship Parametric Design job openings:
Internship Parametric Design jobs near you
Infographic showing various Internship Parametric Design job openings in California as of August 2026, with employment types broken down into 14% Internship, and 86% Full Time. Highlights an 100% In-person job distribution.

Memory Circuit Design Engineer

Intel

Santa Clara, CA • On-site

Full-time

Medical, Retirement, PTO

Re-posted 17 days ago

Intel rating

8.7

Company rating: 8.7 out of 10

Based on 147 frontline employees who took The Breakroom Quiz

19th of 156 rated electronics manufacturers

Job description

Job Details:Job Description: 

The world is transforming - and so is Intel. Intel is a company of bold and curious inventors and problem solvers who create some of the most astounding technology advancements and experiences in the world. With a legacy of relentless innovation and a commitment to bring smart, connected devices to every person on Earth, our diverse and brilliant teams are continually searching for tomorrow's technology and revel in the challenge that changing the world for the better brings. We work every single day to design and manufacture silicon products that empower people's digital lives. Come join us and do something wonderful.

The Advanced Design (AD) team is part of Intel's larger Design Technology Platform (DTP) Organization and is focused on pathfinding and development of advanced memory technology. These circuits enable best-in-class memory collateral, IP and innovative product design across all generations of Intel process technology. At Intel, DTP is one of the key pillars enabling Intel to deliver winning products in the marketplace. Your work will directly enable Intel's internal and external customers to get to the market faster with products that include high-performance, high-density, low-power memory at the leading edge of the technology curve and implemented in Intel's advanced CMOS process technologies.

You will be partnering with and leveraging domain experts across various areas of technology development, EDA vendors and product design teams to develop and deliver high-quality industry-leading memory technology collaterals and to drive circuit innovations that enable next generation high-performance, high-density, low-power embedded memory designs on Intel advanced CMOS process technologies. In this position your responsibilities will include, but may not be limited to:

  • Memory pathfinding activities and power, performance and area (PPA) optimization through design technology co-optimization (DTCO) and product design enablement.
  • Memory bit-cell and complex periphery IC layout and automation.
  • Memory array/IP design, memory circuit innovation, test-chip design.
  • Pre-Si verification, post-Si validation and debugging to enable yield and parametric tracking/ramp.
Qualifications:

You must possess the minimum qualifications listed below to interview for this position. Preferred qualifications are not required but may work to your advantage during the interview process.
Minimum Qualifications:
Master degree in Electrical Engineering, Computer Engineering, Electrical and Computer Engineering, or a related discipline, including 4+ years of professional experience gained through either internships or full-time employment Or a PhD in Electrical Engineering, Computer Engineering, Electrical and Computer Engineering, or a related discipline.
Technical Experience:

  • Design, characterization, and verification of custom memory circuits such as SRAM, Register Files or ROM.
  • Design trade-offs between power, performance, and area (PPA).
  • Custom digital circuit design, simulation, layout design, and verification.
  • Knowledge of EDA tools used for custom digital and memory circuit design.

Preferred Qualifications:

  • PhD with 1-2 years of professional experience gained through either internships or full-time employment.
  • Design technology co-optimization (DTCO).
  • Post-Si validation experience.
  • Knowledge of the CMOS ASIC design flow.
Job Type:Experienced HireShift:Shift 1 (United States of America)Primary Location: US, Oregon, HillsboroAdditional Locations:US, Arizona, Phoenix, US, California, Santa Clara, US, Texas, AustinBusiness group:Intel Foundry strives to make every facet of semiconductor manufacturing state-of-the-art while delighting our customers -- from delivering cutting-edge silicon process and packaging technology leadership for the AI era, enabling our customers to design leadership products, global manufacturing scale and supply chain, through the continuous yield improvements to advanced packaging all the way to final test and assembly. We ensure our foundry customers' products receive our utmost focus in terms of service, technology enablement and capacity commitments. Employees in the Foundry Technology Manufacturing are part of a worldwide factory network that designs, develops, manufactures, and assembly/test packages the compute devices to improve the lives of every person on Earth.Posting Statement:All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.Position of TrustN/ABenefits

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel.

Annual Salary Range for jobs which could be performed in the US: $122,440.00-232,190.00 USDThe range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.

*

ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.

What Intel employees say

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Benefits

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Workplace

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About Intel

Sourced by ZipRecruiter

Intel strives to make every facet of semiconductor manufacturing state-of-the-art -- from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support. Employees in the Technology and Manufacturing Group are part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moore's Law to bring smart, connected devices to every person on Earth

Industry

Manufacturing

Company size

10,000+ Employees

Headquarters location

Santa Clara, CA, US

Year founded

1968

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