1

Internship Ic Layout Designer Jobs (NOW HIRING)

Analog Layout Engineer

Santa Clara, CA · On-site

$237K/yr

Senior layout designer, will be responsible for layout of high-performance analog cores such as ... Responsibilities include leading IC layout of cutting-edge high-performance, high-speed CMOS ...

Texas Instruments is seeking an experienced Layout Designer to join our team! Responsibilities ... Associate's degree in Engineering or related field of study or program certificate in Advanced IC ...

Texas Instruments is seeking an experienced Layout Designer to join our team! Responsibilities ... Associate's degree in Engineering or related field of study or program certificate in Advanced IC ...

Texas Instruments is seeking an experienced Layout Designer to join our team! Responsibilities ... Associate's degree in Engineering or related field of study or program certificate in Advanced IC ...

Staff Layout Designer

San Jose, CA · On-site

$72 - $122/hr

As a Staff Layout Designer, you will develop and prepare multi-dimensional layouts. You will ... IC layout design experience with NAND, DRAM and/or SRAM * Programming skills and AI experience ...

$134K - $201K/yr

Lead Analog IC Layout Engineer About the ATE Group: The Automatic Test Equipment (ATE) organization ... As a Lead Designer, Layout, you hold a senior technical position working on our most complex layout ...

Texas Instruments is seeking an experienced Layout Designer to join our team! Responsibilities ... Associate's degree in Engineering or related field of study or program certificate in Advanced IC ...

Strong communication skills and ability to collaborate with designers and layout teams Who You Will Be Working With: IC Enable benefits include Medical, Dental, Vision and Ancillary benefits, 401K ...

Principal IC Layout Engineer About the ATE Group: The Automatic Test Equipment (ATE) organization ... As a Principal Designer, Layout, you are a recognized expert within ADI, working on uniquely ...

This SkyWater Layout Principal Designer will primarily lead custom layout and Electronic Design ... Expert in custom layout design using IC EDA tool-assisted design flow such as Cadence and Siemens ...

next page

Showing results 1-20

Internship Ic Layout Designer information

See salary details

$6

$16

$23

How much do internship ic layout designer jobs pay per hour?

As of Jun 17, 2026, the average hourly pay for internship ic layout designer in the United States is $16.33, according to ZipRecruiter salary data. Most workers in this role earn between $14.42 and $19.23 per hour, depending on experience, location, and employer.
What cities are hiring for Internship Ic Layout Designer jobs? Cities with the most Internship Ic Layout Designer job openings:
What are the most commonly searched types of Ic Layout Designer jobs? The most popular types of Ic Layout Designer jobs are:
What states have the most Internship Ic Layout Designer jobs? States with the most job openings for Internship Ic Layout Designer jobs include:
Analog Layout Engineer

Analog Layout Engineer

Glow Networks

Santa Clara, CA • On-site

$237K/yr

Full-time

Posted 8 days ago


Job description

Role: Analog Layout Engineer
Location: Santa Clara, CA (Remote Option available)
Duration: Long Term
Responsibilities:
Senior layout designer, will be responsible for layout of high-performance analog cores such as analog-to-digital converters, digital-to-analog converters, PLL, transceivers, etc.
Responsibilities include leading IC layout of cutting-edge high-performance, high-speed CMOS integrated circuits in foundry CMOS process nodes in 5nm, 7nm, 16nm, 28nm, 40nm and 65nm following best practices from the industry.
Qualifications
Thorough knowledge of industry standard EDA tools from Cadence, Mentor and Synopsys.
Must be able to set up LVS, DRC, ERC environments and debug verification issues using Cadence and Mentor tools.
Experience with layout of high-performance analog blocks such as analog to digital converters, references, digital to analog converters, PLL etc. desired.
Experience with floor planning, block level routing and top-level chip assembly.
Knowledge of high-performance analog layout techniques such as common centroid layout, shielding, use of dummy devices, thermal aware layout with consideration for electromigration.
Demonstrated experience with analog layout for silicon chips in mass production.
Experience with FinFET process nodes preferred
Experience working with distributed design teams a plus.
Knowledge of skill code and layout automation is a plus.
Self-starter with the ability to define and adhere to a schedule.
Must possess strong written and verbal communication skills.
10+ years' experience in high performance analog layout in advanced CMOS processes.