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Internship Asic Rtl Design Engineer Jobs in Simi Valley, CA

Apple

Wireless SoC Design Engineer

Los Angeles, CA

$175K - $308K/yr

... RTL design and integration, Emulation, Design Verification, Test and Validation, and FW/SW ... This is a highly visible role, where you will be at the center of the ASIC design efforts ...

Apple

Wireless SoC Design Engineer

Los Angeles, CA

$122K - $214K/yr

... RTL design and integration, Emulation, Design Verification, Test and Validation, and FW/SW ... This is a highly visible role, where you will be at the center of the ASIC design efforts ...

Apple

Wireless SoC Design Engineer

Los Angeles, CA

$122K - $214K/yr

... RTL design and integration, Emulation, Design Verification, Test and Validation, and FW/SW ... This is a highly visible role, where you will be at the center of the ASIC design efforts ...

Apple

Wireless SoC Design Engineer

Los Angeles, CA

$175K - $308K/yr

... RTL design and integration, Emulation, Design Verification, Test and Validation, and FW/SW ... This is a highly visible role, where you will be at the center of the ASIC design efforts ...

Apple

Wireless SoC Design Engineer

Los Angeles, CA

$122K - $214K/yr

... RTL design and integration, Emulation, Design Verification, Test and Validation, and FW/SW ... This is a highly visible role, where you will be at the center of the ASIC design efforts ...

Apple

Wireless SoC Design Engineer

Los Angeles, CA

$175K - $308K/yr

... RTL design and integration, Emulation, Design Verification, Test and Validation, and FW/SW ... This is a highly visible role, where you will be at the center of the ASIC design efforts ...

Apple

Wireless SoC Design Engineer

Los Angeles, CA

$175K - $308K/yr

... RTL design and integration, Emulation, Design Verification, Test and Validation, and FW/SW ... This is a highly visible role, where you will be at the center of the ASIC design efforts ...

USPRO

Senior Digital Design Engineer

Glendale, CA

$85/hr

Job Title : Sr FPGA Engineer Location : El Segundo, CA or Cedar Rapids, IA Pay Range : $85.00/hour ... Proficient in VHDL/Verilog for FPGA/ASIC design and implementation. * Experience in digital circuit ...

USPRO

Senior Digital Design Engineer

Glendale, CA

$85/hr

Job Title : Sr FPGA Engineer Location : El Segundo, CA or Cedar Rapids, IA Pay Range : $85.00/hour ... Proficient in VHDL/Verilog for FPGA/ASIC design and implementation. * Experience in digital circuit ...

USPRO

Senior Digital Design Engineer

Los Angeles, CA

$85/hr

Job Title : Sr FPGA Engineer Location : El Segundo, CA or Cedar Rapids, IA Pay Range : $85.00/hour ... Proficient in VHDL/Verilog for FPGA/ASIC design and implementation. * Experience in digital circuit ...

USPRO

Senior Digital Design Engineer

Los Angeles, CA

$85/hr

Job Title : Sr FPGA Engineer Location : El Segundo, CA or Cedar Rapids, IA Pay Range : $85.00/hour ... Proficient in VHDL/Verilog for FPGA/ASIC design and implementation. * Experience in digital circuit ...

USPRO

Senior Digital Design Engineer

Los Angeles, CA

$85/hr

Job Title : Sr FPGA Engineer Location : El Segundo, CA or Cedar Rapids, IA Pay Range : $85.00/hour ... Proficient in VHDL/Verilog for FPGA/ASIC design and implementation. * Experience in digital circuit ...

USPRO

Senior Digital Design Engineer

Glendale, CA

$85/hr

Job Title : Sr FPGA Engineer Location : El Segundo, CA or Cedar Rapids, IA Pay Range : $85.00/hour ... Proficient in VHDL/Verilog for FPGA/ASIC design and implementation. * Experience in digital circuit ...

USPRO

Senior Digital Design Engineer

Burbank, CA

$85/hr

Job Title : Sr FPGA Engineer Location : El Segundo, CA or Cedar Rapids, IA Pay Range : $85.00/hour ... Proficient in VHDL/Verilog for FPGA/ASIC design and implementation. * Experience in digital circuit ...

USPRO

Senior Digital Design Engineer

Malibu, CA

$85/hr

Job Title : Sr FPGA Engineer Location : El Segundo, CA or Cedar Rapids, IA Pay Range : $85.00/hour ... Proficient in VHDL/Verilog for FPGA/ASIC design and implementation. * Experience in digital circuit ...

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Showing results 21-40

All JobsAsic Rtl Design Engineer JobsInternship Asic Rtl Design Engineer JobsInternship Asic Rtl Design Engineer Jobs in Simi Valley, CA

Internship Asic Rtl Design Engineer information

See Simi Valley, CA salary details

$97K

$155K

$208.5K

How much do internship asic rtl design engineer jobs pay per year?

As of Aug 6, 2026, the average yearly pay for internship asic rtl design engineer in Simi Valley, CA is $155,046.00, according to ZipRecruiter salary data. Most workers in this role earn between $135,700.00 and $185,800.00 per year, depending on experience, location, and employer.

What does an internship ASIC RTL design engineer do?

As an ASIC RTL Design Engineering intern, you'll typically work on tasks such as writing and verifying RTL code using languages like Verilog or VHDL, assisting with simulation and debugging, and collaborating closely with senior engineers on real design blocks. Interns often participate in design reviews, update documentation, and may get hands-on experience with synthesis and timing analysis tools. This role is highly collaborative and provides exposure to the complete ASIC development cycle, making it an excellent opportunity to build foundational skills and gain insight into industry-standard methodologies.

What are the key skills and qualifications needed to thrive as an internship ASIC RTL design engineer?

To thrive as an Internship ASIC RTL Design Engineer, you need a solid understanding of digital logic design, computer architecture, and proficiency in HDL languages like Verilog or VHDL, typically supported by coursework in electrical or computer engineering. Familiarity with industry-standard EDA tools such as Synopsys, Cadence, or Mentor Graphics, and simulation environments is highly valuable. Strong analytical thinking, attention to detail, and effective communication skills help interns collaborate with teams and learn quickly in a fast-paced environment. These skills and qualities are essential for contributing to complex chip design projects and ensuring accuracy and efficiency in RTL development.

What is an internship ASIC RTL design engineer?

An Internship ASIC RTL (Register Transfer Level) Design Engineer is a student or recent graduate who assists in designing and developing digital integrated circuits (ICs) using hardware description languages like Verilog or VHDL. They work under the guidance of senior engineers to create, simulate, and verify RTL code for ASIC (Application Specific Integrated Circuit) projects. The role provides hands-on experience with the chip design process, including synthesis, timing analysis, and verification. Interns gain valuable exposure to industry-standard tools and methodologies, helping them prepare for a full-time engineering career.

What is the difference between Internship Asic Rtl Design Engineer vs Asic Verification Engineer?

AspectInternship Asic Rtl Design EngineerAsic Verification Engineer
CredentialsTypically pursuing or recently completed a degree in Electrical Engineering or Computer EngineeringSimilar educational background, often with additional coursework in verification methodologies
Work EnvironmentInternship setting, supervised, focused on learning and assisting in RTL design tasksFull-time role, focused on testing and verifying RTL designs
Industry UsageUsed in semiconductor and chip design companies during early career stagesCommon in companies developing complex integrated circuits and chips

The Internship Asic Rtl Design Engineer focuses on assisting in RTL design tasks during an internship, emphasizing learning and support. In contrast, the Asic Verification Engineer is responsible for verifying RTL designs to ensure functionality. Both roles require similar educational backgrounds but differ in responsibilities and work environment, with verification roles being more advanced and permanent.

What job categories do people searching Internship Asic Rtl Design Engineer jobs in Simi Valley, CA look for? The top searched job categories for Internship Asic Rtl Design Engineer jobs in Simi Valley, CA are:
What cities near Simi Valley, CA are hiring for Internship Asic Rtl Design Engineer jobs? Cities near Simi Valley, CA with the most Internship Asic Rtl Design Engineer job openings:
Internship Asic Rtl Design Engineer jobs near you
Infographic showing various Internship Asic Rtl Design Engineer job openings in Simi Valley, CA as of August 2026, with employment types broken down into 72% Full Time, and 28% Contract. Highlights an 73% In-person, and 27% Remote job distribution, with an average salary of $155,046 per year, or $74.5 per hour.

Senior ASIC Physical Design Engineer

K2 Space

Los Angeles, CA • On-site

$170K - $250K/yr

Full-time

Re-posted 11 days ago

Job description

K2 is building the largest and highest-power satellites ever flown, unlocking performance levels previously out of reach across every orbit. Backed by $450M from leading investors including Altimeter Capital, Redpoint Ventures, T. Rowe Price, Lightspeed Venture Partners, Alpine Space Ventures, and others – with an additional $500M in signed contracts across commercial and US government customers – we're mass-producing the highest-power satellite platforms ever built for missions from LEO to deep space.

The rise of heavy-lift launch vehicles is shifting the industry from an era of mass constraint to one of mass abundance, and we believe this new era demands a fundamentally different class of spacecraft. Engineered to survive the harshest radiation environments and to fully capitalize on today's and tomorrow's massive rockets, K2 satellites deliver unmatched capability at constellation scale and across multiple orbits.

With multiple launches planned through 2026 and 2027, we're Building Bigger to develop the solar system and become a Kardashev Type II (K2) civilization. If you are a motivated individual who thrives in a fast-paced environment and you're excited about contributing to the success of a groundbreaking Series C space startup, we'd love for you to apply.

The Role

We are seeking a Senior ASIC Physical Design Engineer to help implement advanced SoCs that power next-generation satellite and space systems. In this role, you will contribute to the full physical design flow—from synthesis to GDSII—working closely with architecture, RTL, verification, and packaging teams. You'll be a key contributor in achieving timing closure, optimizing PPA, and supporting design integration with external partners. You will be part of a collaborative design team developing state-of-the-art mixed-signal SoCs to be hosted on some of the largest, most powerful, rapidly designed and rapidly manufactured satellites ever deployed in space. In your first 6 months, you will develop and implement new SoC sub-systems for satellite communications and beyond. In your first two years, you will have contributed to developing cutting-edge SoCs that will fly in space. 

Responsibilities

  • Execute the complete physical design flow for complex SoC blocks and top-level integration, including synthesis, floorplanning, place & route, CTS, STA, and physical verification.
  • Perform timing closure and optimization across multiple corners and modes using industry-standard tools.
  • Collaborate with front-end, verification, and DFT teams to ensure clean handoff and predictable convergence.
  • Work with external physical design service providers and internal leads to review deliverables, resolve issues, and ensure schedule alignment.
  • Develop and maintain scripts and automation to improve flow efficiency and consistency.
  • Support physical sign-off activities including DRC/LVS, IR drop, EM, and power analysis.
  • Assist in chip-level integration, ECOs, and tapeout preparation.
  • Contribute to methodology development, tool evaluation, and flow documentation.
  • Support your product through production and spaceflight.

Required Qualifications 

  • Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or related field.
  • 5–10 years of experience in ASIC physical design for complex SoCs.
  • Hands-on experience with industry-standard tools (Synopsys ICC2/Fusion Compiler, Cadence Innovus, or equivalent).
  • Strong understanding of timing analysis, power optimization, and physical verification flows.
  • Experience with hierarchical or flat SoC design methodologies.
  • Familiarity with FinFET technologies.
  • Working knowledge of DFT, UPF/CPF power intent, and ECO implementation.
  • Strong problem-solving skills and ability to work cross-functionally in fast-paced environments.

Preferred Qualifications 

  • Exposure to radiation-hardened or space-qualified ASICs.
  • Experience with chip-package co-design or advanced packaging (2.5D/3D).
  • Familiarity with physical design service vendor management or offshore collaboration.
  • Experience with sign-off through TSMC.
  • Experience with Gate-All-Around technologies.
  • Experience working in cross-functional, geographically distributed teams.

Compensation and Benefits:

  • Base salary range for this role is $170,000 – $250,000 + equity in the company
  • Salary will be based on several factors including, but not limited to: knowledge and skills, education, and experience level
  • Comprehensive benefits package including paid time off, medical/dental/vision/ coverage, life insurance, paid parental leave, and many other perks

If you don't meet 100% of the preferred skills and experience, we encourage you to still apply! Building a spacecraft unlike any other requires a team unlike any other and non-traditional career twists and turns are encouraged!

If you need a reasonable accommodation as part of your application for employment or interviews with us, please let us know.

Export Compliance

As defined in the ITAR, "U.S. Persons" include U.S. citizens, lawful permanent residents (i.e., Green Card holders), and certain protected individuals (e.g., refugees/asylees, American Samoans). Please consult with a knowledgeable advisor if you are unsure whether you are a "U.S. Person."

The person hired for this role will have access to information and items controlled by U.S. export control regulations, including the export control regulations outlined in the International Traffic in Arms Regulation (ITAR). The person hired for this role must therefore either be a "U.S. person" as defined by 22 C.F.R. § 120.15 or otherwise eligible for a federally issued export control license.

Equal Opportunity

K2 Space is an Equal Opportunity Employer; employment with K2 Space is governed on the basis of merit, competence and qualifications and will not be influenced in any manner by race, color, religion, gender, national origin/ethnicity, veteran status, disability status, age, sexual orientation, gender identity, marital status, mental or physical disability or any other legally protected status.

K2 Space logo

About K2 Space

Sourced by ZipRecruiter

Industry

Guided missile and space vehicle manufacturing

Company size

11 - 50 Employees

Headquarters location

Los Angeles, CA, US

Year founded

2022

View All K2 Space Jobs