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Internship Asic Rtl Design Engineer Jobs in Hawthorne, CA

SpaceX

Sr. ASIC Design Engineer (Starshield)

Hawthorne, CA · On-site

$160K - $225K/yr

SR. ASIC DESIGN ENGINEER (STARSHIELD) Starshield leverages SpaceX's Starlink technology and launch ... Define micro-architecture, implement the RTL in Verilog/System Verilog, integrate that in top level ...

Apple

Wireless RTL Design Engineer

Los Angeles, CA

$175K - $308K/yr

... RTL design and integration, Emulation, Design Verification, Test and Validation, and FW/SW engineering. Description In this highly visible role, you will be at the center of a silicon design group ...

Apple

Wireless RTL Design Engineer

Los Angeles, CA

$175K - $308K/yr

... RTL design and integration, Emulation, Design Verification, Test and Validation, and FW/SW engineering. Description In this highly visible role, you will be at the center of a silicon design group ...

Apple

Wireless RTL Design Engineer

Los Angeles, CA

$175K - $308K/yr

... RTL design and integration, Emulation, Design Verification, Test and Validation, and FW/SW engineering. Description In this highly visible role, you will be at the center of a silicon design group ...

Apple

Wireless RTL Design Engineer

Los Angeles, CA · On-site

... RTL design and integration, Emulation, Design Verification, Test and Validation, and FW/SW engineering. Description In this highly visible role, you will be at the center of a silicon design group ...

SpaceX

Sr. ASIC Design Engineer (Starshield)

Hawthorne, CA · On-site

$160K - $225K/yr

As an ASIC Design Engineer on the Starshield team, you will be working on advanced development ... Define micro-architecture, implement the RTL in Verilog/System Verilog, integrate that in top level ...

Silvus Technologies

FPGA Design Engineer

Los Angeles, CA · On-site

$100K - $140K/yr

THE OPPORTUNITY Silvus is seeking a Senior FPGA / RTL Design Engineer reporting to the Director of ... Experience with communication systems on FPGA or ASIC designs. COMPENSATION The pay range is NOT a ...

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All JobsAsic Rtl Design Engineer JobsInternship Asic Rtl Design Engineer JobsInternship Asic Rtl Design Engineer Jobs in Hawthorne, CA

Internship Asic Rtl Design Engineer information

See Hawthorne, CA salary details

$95.6K

$152.7K

$205.4K

How much do internship asic rtl design engineer jobs pay per year?

As of Aug 7, 2026, the average yearly pay for internship asic rtl design engineer in Hawthorne, CA is $152,699.00, according to ZipRecruiter salary data. Most workers in this role earn between $133,700.00 and $183,000.00 per year, depending on experience, location, and employer.

What does an internship ASIC RTL design engineer do?

As an ASIC RTL Design Engineering intern, you'll typically work on tasks such as writing and verifying RTL code using languages like Verilog or VHDL, assisting with simulation and debugging, and collaborating closely with senior engineers on real design blocks. Interns often participate in design reviews, update documentation, and may get hands-on experience with synthesis and timing analysis tools. This role is highly collaborative and provides exposure to the complete ASIC development cycle, making it an excellent opportunity to build foundational skills and gain insight into industry-standard methodologies.

What are the key skills and qualifications needed to thrive as an internship ASIC RTL design engineer?

To thrive as an Internship ASIC RTL Design Engineer, you need a solid understanding of digital logic design, computer architecture, and proficiency in HDL languages like Verilog or VHDL, typically supported by coursework in electrical or computer engineering. Familiarity with industry-standard EDA tools such as Synopsys, Cadence, or Mentor Graphics, and simulation environments is highly valuable. Strong analytical thinking, attention to detail, and effective communication skills help interns collaborate with teams and learn quickly in a fast-paced environment. These skills and qualities are essential for contributing to complex chip design projects and ensuring accuracy and efficiency in RTL development.

What is an internship ASIC RTL design engineer?

An Internship ASIC RTL (Register Transfer Level) Design Engineer is a student or recent graduate who assists in designing and developing digital integrated circuits (ICs) using hardware description languages like Verilog or VHDL. They work under the guidance of senior engineers to create, simulate, and verify RTL code for ASIC (Application Specific Integrated Circuit) projects. The role provides hands-on experience with the chip design process, including synthesis, timing analysis, and verification. Interns gain valuable exposure to industry-standard tools and methodologies, helping them prepare for a full-time engineering career.

What is the difference between Internship Asic Rtl Design Engineer vs Asic Verification Engineer?

AspectInternship Asic Rtl Design EngineerAsic Verification Engineer
CredentialsTypically pursuing or recently completed a degree in Electrical Engineering or Computer EngineeringSimilar educational background, often with additional coursework in verification methodologies
Work EnvironmentInternship setting, supervised, focused on learning and assisting in RTL design tasksFull-time role, focused on testing and verifying RTL designs
Industry UsageUsed in semiconductor and chip design companies during early career stagesCommon in companies developing complex integrated circuits and chips

The Internship Asic Rtl Design Engineer focuses on assisting in RTL design tasks during an internship, emphasizing learning and support. In contrast, the Asic Verification Engineer is responsible for verifying RTL designs to ensure functionality. Both roles require similar educational backgrounds but differ in responsibilities and work environment, with verification roles being more advanced and permanent.

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Internship Asic Rtl Design Engineer jobs near you
Infographic showing various Internship Asic Rtl Design Engineer job openings in Hawthorne, CA as of June 2026, with employment types broken down into 1% Internship, 3% As Needed, 77% Full Time, and 19% Contract. Highlights an 96% Physical, 1% Hybrid, and 3% Remote job distribution, with an average salary of $152,699 per year, or $73.4 per hour.

FPGA Design Engineer

Silvus Technologies

Los Angeles, CA • Hybrid

$132K - $182K/yr

Other

Re-posted 17 days ago

Job description

THE OPPORTUNITY

Silvus is seeking a Senior FPGA / RTL Design Engineer reporting to the Director of FPGA Engineering on the FPGA Engineering team. The successful individual in this role will participate in all aspects of the research and development process from concept to field deployment.  FPGA Design Engineers are responsible for the efficient implementation of novel signal processing algorithms for Silvus' MIMO wireless networking products. In addition, they participate in the support and development of FPGA-based designs for our advanced wireless systems R&D.  These are exciting projects targeted to address challenging real-world communication needs. 

The Senior FPGA / RTL Design Engineer position will be based at Silvus headquarters in the heart of vibrant West Los Angeles, CA and is on a hybrid schedule; a minimum of 3 days onsite per week is expected. On-site days are Mondays, Wednesdays, and Thursdays.

The following is a list of at least some of the current essential job functions of the position. Management may assign or reassign duties and responsibilities at any time at its discretion. 

ROLE AND RESPONSIBILITIES

  • Digital design architecting for wireless communication projects.
  • Fixed point design of signal processing blocks while working with systems engineers.
  • RTL coding, simulation, and test bench development.
  • FPGA synthesis and timing closure.
  • Hardware verification and troubleshooting; familiarity with logic analyzers.
  • Provide support to the RF and Software Engineering teams.

REQUIRED QUALIFICATIONS

  • Bachelor of Science degree in Electrical Engineering, Computer Science, or relevant fields.
  • Minimum 6 years of demonstrated experience in FPGA design; 4 years of FPGA design experience with a Master's of Science degree; 2 years of FPGA design experience with a PhD degree.
  • Demonstrated experience with fixed point binary arithmetic and digital signal processing designs.
  • Proven expertise working with multiple clock-domain, high-utilization FPGA designs.
  • Experience with Xilinx FPGAs, SoCs, and the Vivado IDE.
  • NOTE - Must be a U.S. Person (U.S. Citizen, or U.S. Permanent Resident) due to clients under U.S. federal contracts.

PREFERRED KNOWLEDGE, SKILLS, AND ABILITIES

  • Master of Science degree in Electrical Engineering (MSEE).
  • Basic MATLAB skill.
  • Experience with communication systems on FPGA or ASIC designs.

Apply