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Internship Asic Rtl Design Engineer Jobs in Brea, CA

Silvus Technologies

FPGA Design Engineer

Los Angeles, CA · On-site

$100K - $140K/yr

THE OPPORTUNITY Silvus is seeking a Senior FPGA / RTL Design Engineer reporting to the Director of ... Experience with communication systems on FPGA or ASIC designs. COMPENSATION The pay range is NOT a ...

Apple

DDR Design Engineer

Irvine, CA · On-site

As a logic design engineer, you will be involved in all phases of the design, from concept study ... You will provide high-quality RTL description, including assertions, for the design. Use formal ...

Apple

DDR Design Engineer

Irvine, CA · On-site

As a logic design engineer, you will be involved in all phases of the design, from concept study ... You will provide high-quality RTL description, including assertions, for the design. Use formal ...

Apple

Debug SoC Design Engineer

Irvine, CA

$122K - $214K/yr

... RTL design and integration, Emulation, Design Verification, Test and Validation, and FW/SW ... This is a highly visible role, where you will be at the center of the ASIC debug efforts ...

Apple

Debug SoC Design Engineer

Irvine, CA

$175K - $308K/yr

... RTL design and integration, Emulation, Design Verification, Test and Validation, and FW/SW ... This is a highly visible role, where you will be at the center of the ASIC debug efforts ...

Apple

Debug SoC Design Engineer

Irvine, CA

$122K - $214K/yr

... RTL design and integration, Emulation, Design Verification, Test and Validation, and FW/SW ... This is a highly visible role, where you will be at the center of the ASIC debug efforts ...

Apple

Debug SoC Design Engineer

Irvine, CA

$122K - $214K/yr

... RTL design and integration, Emulation, Design Verification, Test and Validation, and FW/SW ... This is a highly visible role, where you will be at the center of the ASIC debug efforts ...

Apple

Debug SoC Design Engineer

Irvine, CA

$175K - $308K/yr

... RTL design and integration, Emulation, Design Verification, Test and Validation, and FW/SW ... This is a highly visible role, where you will be at the center of the ASIC debug efforts ...

Apple

Debug SoC Design Engineer

Irvine, CA

$175K - $308K/yr

... RTL design and integration, Emulation, Design Verification, Test and Validation, and FW/SW ... This is a highly visible role, where you will be at the center of the ASIC debug efforts ...

Apple

Wireless SoC Design Engineer

Los Angeles, CA · On-site

... RTL design and integration, Emulation, Design Verification, Test and Validation, and FW/SW ... This is a highly visible role, where you will be at the center of the ASIC design efforts ...

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Showing results 41-60

All JobsAsic Rtl Design Engineer JobsInternship Asic Rtl Design Engineer JobsInternship Asic Rtl Design Engineer Jobs in Brea, CA

Internship Asic Rtl Design Engineer information

See Brea, CA salary details

$97.4K

$155.6K

$209.2K

How much do internship asic rtl design engineer jobs pay per year?

As of Aug 6, 2026, the average yearly pay for internship asic rtl design engineer in Brea, CA is $155,581.00, according to ZipRecruiter salary data. Most workers in this role earn between $136,200.00 and $186,500.00 per year, depending on experience, location, and employer.

What does an internship ASIC RTL design engineer do?

As an ASIC RTL Design Engineering intern, you'll typically work on tasks such as writing and verifying RTL code using languages like Verilog or VHDL, assisting with simulation and debugging, and collaborating closely with senior engineers on real design blocks. Interns often participate in design reviews, update documentation, and may get hands-on experience with synthesis and timing analysis tools. This role is highly collaborative and provides exposure to the complete ASIC development cycle, making it an excellent opportunity to build foundational skills and gain insight into industry-standard methodologies.

What are the key skills and qualifications needed to thrive as an internship ASIC RTL design engineer?

To thrive as an Internship ASIC RTL Design Engineer, you need a solid understanding of digital logic design, computer architecture, and proficiency in HDL languages like Verilog or VHDL, typically supported by coursework in electrical or computer engineering. Familiarity with industry-standard EDA tools such as Synopsys, Cadence, or Mentor Graphics, and simulation environments is highly valuable. Strong analytical thinking, attention to detail, and effective communication skills help interns collaborate with teams and learn quickly in a fast-paced environment. These skills and qualities are essential for contributing to complex chip design projects and ensuring accuracy and efficiency in RTL development.

What is an internship ASIC RTL design engineer?

An Internship ASIC RTL (Register Transfer Level) Design Engineer is a student or recent graduate who assists in designing and developing digital integrated circuits (ICs) using hardware description languages like Verilog or VHDL. They work under the guidance of senior engineers to create, simulate, and verify RTL code for ASIC (Application Specific Integrated Circuit) projects. The role provides hands-on experience with the chip design process, including synthesis, timing analysis, and verification. Interns gain valuable exposure to industry-standard tools and methodologies, helping them prepare for a full-time engineering career.

What is the difference between Internship Asic Rtl Design Engineer vs Asic Verification Engineer?

AspectInternship Asic Rtl Design EngineerAsic Verification Engineer
CredentialsTypically pursuing or recently completed a degree in Electrical Engineering or Computer EngineeringSimilar educational background, often with additional coursework in verification methodologies
Work EnvironmentInternship setting, supervised, focused on learning and assisting in RTL design tasksFull-time role, focused on testing and verifying RTL designs
Industry UsageUsed in semiconductor and chip design companies during early career stagesCommon in companies developing complex integrated circuits and chips

The Internship Asic Rtl Design Engineer focuses on assisting in RTL design tasks during an internship, emphasizing learning and support. In contrast, the Asic Verification Engineer is responsible for verifying RTL designs to ensure functionality. Both roles require similar educational backgrounds but differ in responsibilities and work environment, with verification roles being more advanced and permanent.

What are popular job titles related to Internship Asic Rtl Design Engineer jobs in Brea, CA? For Internship Asic Rtl Design Engineer jobs in Brea, CA, the most frequently searched job titles are:
What cities near Brea, CA are hiring for Internship Asic Rtl Design Engineer jobs? Cities near Brea, CA with the most Internship Asic Rtl Design Engineer job openings:
Internship Asic Rtl Design Engineer jobs near you

Senior ASIC Emulation Engineer

K2 Space

Los Angeles, CA

$170K - $250K/yr

Full-time

Posted 2 days ago

New

Job description

K2 is building the largest and highest-power satellites ever flown, unlocking performance levels previously out of reach across every orbit. Backed by $450M from leading investors including Altimeter Capital, Redpoint Ventures, T. Rowe Price, Lightspeed Venture Partners, Alpine Space Ventures, and others – with an additional $500M in signed contracts across commercial and US government customers – we're mass-producing the highest-power satellite platforms ever built for missions from LEO to deep space.

The rise of heavy-lift launch vehicles is shifting the industry from an era of mass constraint to one of mass abundance, and we believe this new era demands a fundamentally different class of spacecraft. Engineered to survive the harshest radiation environments and to fully capitalize on today's and tomorrow's massive rockets, K2 satellites deliver unmatched capability at constellation scale and across multiple orbits.

With multiple launches planned through 2026 and 2027, we're Building Bigger to develop the solar system and become a Kardashev Type II (K2) civilization. If you are a motivated individual who thrives in a fast-paced environment and you're excited about contributing to the success of a groundbreaking Series C space startup, we'd love for you to apply.

The Role

We are seeking a Senior ASIC Emulation Engineer who will lead the bring-up, deployment, and optimization of our pre-silicon emulation platforms. You will work closely with architecture, RTL design, DFT, DV, firmware, physical design, and silicon validation teams to enable high‑fidelity hardware/software co-development and accelerate verification cycles. This is a hands-on role with high ownership, deep technical engagement, and the opportunity to shape first‑generation silicon and system methodology.

Responsibilities

  • Build, integrate, and maintain full-chip, multi-chips and system-level emulation models on platforms such as Palladium, ZeBu, or Veloce.
  • Define and evolve emulation strategy, methodology, and workflows across the ASIC organization.
  • Work with RTL engineers to compile, map, and optimize designs for emulation performance, capacity, and stability.
  • Develop and integrate transactors, BFMs, speed adapters, and virtualization interfaces to support diverse system use cases.
  • Support system‑level testing in emulation by enabling full hardware/software integration, validating complex use cases, and ensuring the environment can run representative end‑to‑end workloads.
  • Accelerate overall verification throughput by helping DV team run targeted and high‑value tests in emulation, including adapting DV content and optimizing flows to reduce simulation bottlenecks.
  • Enable firmware, bootloader, driver, and software teams by providing robust emulation platforms and assisting in HW/SW integration debug.
  • Run emulation workloads, triage failures, perform root-cause analysis, and collaborate across design and verification to resolve issues.
  • Maintain and enhance automation for compile flows, regression management, and continuous integration.
  • Participate in architecture reviews, microarchitecture discussions, and influence design-for-emulation best practices.
  • Support silicon bring-up and post-silicon validation through test reuse, diagnostics, and pre/post-silicon correlation.
  • Manage interactions with external IP providers or emulation partners when needed.

Qualifications

  • B.S. or M.S. in Electrical Engineering, Computer Engineering, or related field.
  • 5+ years of experience in ASIC/SoC development, focused on emulation
  • Solid understanding of SystemVerilog, digital logic, RTL flows, DV methodologies, and ASIC development lifecycles.
  • Hands-on expertise with major emulation platforms (Palladium, ZeBu, Veloce), including model build, debug and performance optimization
  • Proficiency with scripting languages (Python, Perl, TCL) for automation and tooling.
  • Experience with hardware/software interfaces, embedded processors, firmware bring-up, and C/C++‑based system-level testing.
  • Familiarity with industry-standard buses and protocols such as APB/AHB/AXI, JTAG, SPI.
  • Experience driving cross-functional debug involving RTL, DV, firmware, physical design, and validation teams.
  • Understanding of pre- and post-silicon debug methodologies and correlation workflows.

Nice to Have

  • Experience with FPGA prototyping platforms (HAPS, Protium, custom FPGA boards).
  • Experience with low-power modes and power-aware emulation.
  • Experience with analog/mixed-signal behavioral models in emulation environments.
  • Experience with SERDES and high-speed data protocols such as PCIe, Ethernet, USB, or multi-gigabit PHYs.

Compensation and Benefits:

  • Base salary range for this role is $170,000 – $250,000 + equity in the company
  • Salary will be based on several factors including, but not limited to: knowledge and skills, education, and experience level
  • Comprehensive benefits package including paid time off, medical/dental/vision/ coverage, life insurance, paid parental leave, and many other perks

If you don't meet 100% of the preferred skills and experience, we encourage you to still apply! Building a spacecraft unlike any other requires a team unlike any other and non-traditional career twists and turns are encouraged!

If you need a reasonable accommodation as part of your application for employment or interviews with us, please let us know.

Export Compliance

As defined in the ITAR, "U.S. Persons" include U.S. citizens, lawful permanent residents (i.e., Green Card holders), and certain protected individuals (e.g., refugees/asylees, American Samoans). Please consult with a knowledgeable advisor if you are unsure whether you are a "U.S. Person."

The person hired for this role will have access to information and items controlled by U.S. export control regulations, including the export control regulations outlined in the International Traffic in Arms Regulation (ITAR). The person hired for this role must therefore either be a "U.S. person" as defined by 22 C.F.R. § 120.15 or otherwise eligible for a federally issued export control license.

Equal Opportunity

K2 Space is an Equal Opportunity Employer; employment with K2 Space is governed on the basis of merit, competence and qualifications and will not be influenced in any manner by race, color, religion, gender, national origin/ethnicity, veteran status, disability status, age, sexual orientation, gender identity, marital status, mental or physical disability or any other legally protected status.

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About K2 Space

Sourced by ZipRecruiter

Industry

Guided missile and space vehicle manufacturing

Company size

11 - 50 Employees

Headquarters location

Los Angeles, CA, US

Year founded

2022

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