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Internship Asic Rtl Design Engineer Jobs in Pasadena, CA

SpaceX

Sr. ASIC Design Engineer (Starshield)

Hawthorne, CA · On-site

$160K - $225K/yr

As an ASIC Design Engineer on the Starshield team, you will be working on advanced development ... Define micro-architecture, implement the RTL in Verilog/System Verilog, integrate that in top level ...

Silvus Technologies

FPGA Design Engineer

Los Angeles, CA · On-site

$100K - $140K/yr

THE OPPORTUNITY Silvus is seeking a Senior FPGA / RTL Design Engineer reporting to the Director of ... Experience with communication systems on FPGA or ASIC designs. COMPENSATION The pay range is NOT a ...

K2 Space

Senior ASIC Emulation Engineer

Los Angeles, CA · On-site

$170K - $250K/yr

You will work closely with architecture, RTL design, DFT, DV, firmware, physical design, and ... the ASIC organization. * Work with RTL engineers to compile, map, and optimize designs for ...

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All JobsAsic Rtl Design Engineer JobsInternship Asic Rtl Design Engineer JobsInternship Asic Rtl Design Engineer Jobs in Pasadena, CA

Internship Asic Rtl Design Engineer information

See Pasadena, CA salary details

$102.5K

$163.8K

$220.3K

How much do internship asic rtl design engineer jobs pay per year?

As of Aug 21, 2026, the average yearly pay for internship asic rtl design engineer in Pasadena, CA is $163,834.00, according to ZipRecruiter salary data. Most workers in this role earn between $143,400.00 and $196,300.00 per year, depending on experience, location, and employer.

What is an internship ASIC RTL design engineer?

An Internship ASIC RTL (Register Transfer Level) Design Engineer is a student or recent graduate who assists in designing and developing digital integrated circuits (ICs) using hardware description languages like Verilog or VHDL. They work under the guidance of senior engineers to create, simulate, and verify RTL code for ASIC (Application Specific Integrated Circuit) projects. The role provides hands-on experience with the chip design process, including synthesis, timing analysis, and verification. Interns gain valuable exposure to industry-standard tools and methodologies, helping them prepare for a full-time engineering career.

What does an internship ASIC RTL design engineer do?

As an ASIC RTL Design Engineering intern, you'll typically work on tasks such as writing and verifying RTL code using languages like Verilog or VHDL, assisting with simulation and debugging, and collaborating closely with senior engineers on real design blocks. Interns often participate in design reviews, update documentation, and may get hands-on experience with synthesis and timing analysis tools. This role is highly collaborative and provides exposure to the complete ASIC development cycle, making it an excellent opportunity to build foundational skills and gain insight into industry-standard methodologies.

What are the key skills and qualifications needed to thrive as an internship ASIC RTL design engineer?

To thrive as an Internship ASIC RTL Design Engineer, you need a solid understanding of digital logic design, computer architecture, and proficiency in HDL languages like Verilog or VHDL, typically supported by coursework in electrical or computer engineering. Familiarity with industry-standard EDA tools such as Synopsys, Cadence, or Mentor Graphics, and simulation environments is highly valuable. Strong analytical thinking, attention to detail, and effective communication skills help interns collaborate with teams and learn quickly in a fast-paced environment. These skills and qualities are essential for contributing to complex chip design projects and ensuring accuracy and efficiency in RTL development.

What is the difference between Internship Asic Rtl Design Engineer vs Asic Verification Engineer?

AspectInternship Asic Rtl Design EngineerAsic Verification Engineer
CredentialsTypically pursuing or recently completed a degree in Electrical Engineering or Computer EngineeringSimilar educational background, often with additional coursework in verification methodologies
Work EnvironmentInternship setting, supervised, focused on learning and assisting in RTL design tasksFull-time role, focused on testing and verifying RTL designs
Industry UsageUsed in semiconductor and chip design companies during early career stagesCommon in companies developing complex integrated circuits and chips

The Internship Asic Rtl Design Engineer focuses on assisting in RTL design tasks during an internship, emphasizing learning and support. In contrast, the Asic Verification Engineer is responsible for verifying RTL designs to ensure functionality. Both roles require similar educational backgrounds but differ in responsibilities and work environment, with verification roles being more advanced and permanent.

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Senior FPGA Design Engineer job opportunity at Fullerton, CA

Indotronix International Corporation

Fullerton, CA • On-site

$113.63/hr

Contractor

Posted 15 days ago

Job description

Indotronix is seeking a Senior FPGA Design Engineer for a Job Opportunity in Fullerton, CA
 
Job Title: Senior FPGA Design Engineer
Location:  Fullerton, CA
Duration:  12 Months Contract
Pay Rate:  $113.63/hr on W2
 
Note: Need Active Secret clearance at start  
 
Job Description
Design & Architecture:
- Requirements capture and development of FPGA/ASIC digital architectures  
- RTL design and implementation in VHDL or Verilog  
- Timing analysis and closure on high‑speed digital systems  
- Resource trade‑off analysis and design optimization  
 
Verification:
- Testbench development using VHDL or SystemVerilog / UVM  
- Functional verification of RTL blocks and subsystems  
- Support constrained-random, functional coverage, and best‑practice verification methodologies  
 
Integration & Lab Work:
- Hands-on FPGA/ASIC validation using advanced lab equipment  
- Work within secure, air‑gapped environments for system bring-up  
- Integration support with multidisciplinary engineering teams  
 
Required Qualifications
- Active Secret clearance at start  
- Bachelor’s degree in Electrical Engineering, Computer Engineering, or related field  
- Expertise in FPGA design and/or verification  
- Strong VHDL experience  
- Proficiency with Intel/Altera FPGA tools (preferred), Modelsim, Synopsys, and/or FPGA vendor toolchains  
- Experience with high‑speed digital systems, interfaces, and signal processing  
- Ability to work independently and communicate clearly in documentation and presentations  
- Strong hands‑on lab experience (non‑negotiable)  
 
Desired Skills
- SystemVerilog + UVM verification  
- ASIC experience (nice-to-have)  
- Design-for-Test (DFT) and manufacturability knowledge  
- Unix/Linux, scripting, C/C++, or Perl experience  
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About Indotronix

Sourced by ZipRecruiter

In 1986, Indotronix established itself in the staffing space. 22 years later, Avani entered the scene, offering consulting and technology development. Finally, in 2016, the two joined forces to begin delivering talent across all areas, from Staffing to Consulting to unique platform development.

Industry

Recruiting and staffing services

Company size

1,001 - 5,000 Employees

Headquarters location

Rochester, NY, US

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