ZipRecruiter

Log In

1

Internship Asic Rtl Design Engineer Jobs in Pasadena, CA

Astrolab

Staff FPGA Engineer

Hawthorne, CA

$125K - $172K/yr

We work collaboratively across engineering disciplines to deliver reliable, high-performance ... The ideal candidate has 10+ years of experience in FPGA development including RTL design ...

Astrolab

Principal FPGA Engineer

Hawthorne, CA · Hybrid

$141K - $172K/yr

The Principal FPGA Engineer will participate in all aspects of the development and test of avionics ... The ideal candidate has 15+ years of experience in FPGA firmware development including RTL design ...

K2 Space

Solar Design Engineer

Los Angeles, CA · On-site

$100K - $140K/yr

As a Solar Engineer, you will contribute to the design, manufacturing, testing, and deployment of ... Internship in at least one of: photovoltaics, power systems, or materials characterization * Hands ...

Astrolab

Principal FPGA Engineer

Hawthorne, CA · On-site

$203K - $243K/yr

Principal FPGA Engineer Department: Avionics Employment Type: Full Time Location: Hawthorne ... The ideal candidate has 15+ years of experience in FPGA firmware development including RTL design ...

Ashby

Design Engineer - Americas

Los Angeles, CA · Remote

$126K - $250K/yr

You have 2+ years of continuous experience (e.g., internships don't count) as an Engineer or a Designer. You have good proficiency in both Design and Engineering, with exceptional proficiency in the ...

Astrolab

Principal FPGA Engineer

Hawthorne, CA · Hybrid

$203K - $243K/yr

The Principal FPGA Engineer will participate in all aspects of the development and test of avionics ... The ideal candidate has 15+ years of experience in FPGA firmware development including RTL design ...

Astrolab

Staff FPGA Engineer

Hawthorne, CA · On-site

$170K - $226K/yr

We work collaboratively across engineering disciplines to deliver reliable, high-performance ... The ideal candidate has 10+ years of experience in FPGA development including RTL design ...

K2 Space

Solar Design Engineer

Los Angeles, CA · On-site

$100K - $140K/yr

As a Solar Engineer, you will contribute to the design, manufacturing, testing, and deployment of ... Internship or research experience with solar arrays or power systems for space applications

K2 Space

Solar Design Engineer

Los Angeles, CA

$100K - $140K/yr

As a Solar Engineer, you will contribute to the design, manufacturing, testing, and deployment of ... Internship or research experience with solar arrays or power systems for space applications

Astrolab

Staff FPGA Engineer

Hawthorne, CA · On-site

$170K - $226K/yr

Staff FPGA Engineer Department: Avionics Employment Type: Full Time Location: Hawthorne, California ... The ideal candidate has 10+ years of experience in FPGA development including RTL design ...

SpaceX

Harness Design Engineer (Starshield)

Hawthorne, CA · On-site

$115K - $140K/yr

HARNESS DESIGN ENGINEER (STARSHIELD) Starshield leverages SpaceX's satellite technology and launch ... Experience with electro-mechanical wire harness design or manufacturing (includes internships ...

Maesa

Design Engineer Co-Op

Los Angeles, CA · On-site

$20 - $21/hr

Co-Op - Design Engineer Location: Los Angeles, CA Start Date: July 2026 (6-Month Program) About ... Familiarity with SolidWorks or other 3D CAD software (coursework or internship experience a plus)

Maesa

Design Engineer Co-Op

Los Angeles, CA · On-site

$20 - $21/hr

Co-Op - Design Engineer Location: Los Angeles, CA Start Date: July 2026 (6-Month Program) About ... Familiarity with SolidWorks or other 3D CAD software (coursework or internship experience a plus)

previous page

Showing results 41-60

All JobsAsic Rtl Design Engineer JobsInternship Asic Rtl Design Engineer JobsInternship Asic Rtl Design Engineer Jobs in Pasadena, CA

Internship Asic Rtl Design Engineer information

See Pasadena, CA salary details

$102.5K

$163.8K

$220.3K

How much do internship asic rtl design engineer jobs pay per year?

As of Aug 21, 2026, the average yearly pay for internship asic rtl design engineer in Pasadena, CA is $163,834.00, according to ZipRecruiter salary data. Most workers in this role earn between $143,400.00 and $196,300.00 per year, depending on experience, location, and employer.

What is an internship ASIC RTL design engineer?

An Internship ASIC RTL (Register Transfer Level) Design Engineer is a student or recent graduate who assists in designing and developing digital integrated circuits (ICs) using hardware description languages like Verilog or VHDL. They work under the guidance of senior engineers to create, simulate, and verify RTL code for ASIC (Application Specific Integrated Circuit) projects. The role provides hands-on experience with the chip design process, including synthesis, timing analysis, and verification. Interns gain valuable exposure to industry-standard tools and methodologies, helping them prepare for a full-time engineering career.

What does an internship ASIC RTL design engineer do?

As an ASIC RTL Design Engineering intern, you'll typically work on tasks such as writing and verifying RTL code using languages like Verilog or VHDL, assisting with simulation and debugging, and collaborating closely with senior engineers on real design blocks. Interns often participate in design reviews, update documentation, and may get hands-on experience with synthesis and timing analysis tools. This role is highly collaborative and provides exposure to the complete ASIC development cycle, making it an excellent opportunity to build foundational skills and gain insight into industry-standard methodologies.

What are the key skills and qualifications needed to thrive as an internship ASIC RTL design engineer?

To thrive as an Internship ASIC RTL Design Engineer, you need a solid understanding of digital logic design, computer architecture, and proficiency in HDL languages like Verilog or VHDL, typically supported by coursework in electrical or computer engineering. Familiarity with industry-standard EDA tools such as Synopsys, Cadence, or Mentor Graphics, and simulation environments is highly valuable. Strong analytical thinking, attention to detail, and effective communication skills help interns collaborate with teams and learn quickly in a fast-paced environment. These skills and qualities are essential for contributing to complex chip design projects and ensuring accuracy and efficiency in RTL development.

What is the difference between Internship Asic Rtl Design Engineer vs Asic Verification Engineer?

AspectInternship Asic Rtl Design EngineerAsic Verification Engineer
CredentialsTypically pursuing or recently completed a degree in Electrical Engineering or Computer EngineeringSimilar educational background, often with additional coursework in verification methodologies
Work EnvironmentInternship setting, supervised, focused on learning and assisting in RTL design tasksFull-time role, focused on testing and verifying RTL designs
Industry UsageUsed in semiconductor and chip design companies during early career stagesCommon in companies developing complex integrated circuits and chips

The Internship Asic Rtl Design Engineer focuses on assisting in RTL design tasks during an internship, emphasizing learning and support. In contrast, the Asic Verification Engineer is responsible for verifying RTL designs to ensure functionality. Both roles require similar educational backgrounds but differ in responsibilities and work environment, with verification roles being more advanced and permanent.

What are popular job titles related to Internship Asic Rtl Design Engineer jobs in Pasadena, CA?

For Internship Asic Rtl Design Engineer jobs in Pasadena, CA, the most frequently searched job titles are:

What job categories do people searching Internship Asic Rtl Design Engineer jobs in Pasadena, CA look for?

The top searched job categories for Internship Asic Rtl Design Engineer jobs in Pasadena, CA are:

What cities near Pasadena, CA are hiring for Internship Asic Rtl Design Engineer jobs?

Cities near Pasadena, CA with the most Internship Asic Rtl Design Engineer job openings:

Internship Asic Rtl Design Engineer jobs near you

Staff FPGA Engineer

Astrolab

Hawthorne, CA

$125K - $172K/yr

Full-time

Medical, Dental, Vision, Retirement, PTO

Re-posted 20 days ago

Job description

Venturi Astrolab, Inc. (Astrolab) is pioneering new ways to explore and operate on distant planetary bodies. We are focused on designing, building, and operating a fleet of multi-purpose commercial planetary rovers to extend and enhance humanity's presence in the solar system. We are seeking motivated, creative, and exceptional people to join our team. 
The Avionics team is responsible for all aspects of the electrical systems and hardware on Astrolab's electric rover vehicles and ground support equipment. We work collaboratively across engineering disciplines to deliver reliable, high-performance electronics that directly support flight and mission operations. 
The Staff FPGA Engineer will lead the architecture, development, and verification of avionics FPGA RTL designs for Astrolab rovers. This role owns FPGA design from initial concept and requirements definition through verification, integration, and flight readiness. The ideal candidate has 10+ years of experience in FPGA development including RTL design, simulation, analysis, verification, and hardware testing in complex, high reliability systems. 
This position will report to the Director of Avionics Engineering and will be based in our Hawthorne, CA office. 
  • Own FPGA RTL development from clean sheet architecture through qualification and flight 
  • Define FPGA logical architecture and requirements in collaboration with cross-functional engineering teams, including HW and embedded software interfaces 
  • Develop FPGA RTL for Microsemi, Xilinx, or similar devices using SystemVerilog or VHDL 
  • Perform comprehensive design verification, including simulations, test benches, timing closure, resource analysis, and hardware validation 
  • Lead design reviews, ensure requirement traceability, and create clear documentation for FPGA operation and integration with other software and FPGA systems 
  • Develop and execute test campaigns ranging from unit-level validation to system-level integration and testing 
  • Support integration, bring up, and troubleshooting during system-level and flight test activities 
  • Bachelor of Science degree in Computer Engineering, Electrical Engineering, or equivalent 
  • 10+ years of experience in FPGA RTL architecture, development, verification, deployment, and lifecycle support 
  • Strong proficiency in SystemVerilog or VHDL 
  • Proficiency in at least one scripting language such as TCL, shell, or Python 
  • Experience with advanced verification methodologies, timing analysis, and stability analysis 
  • Ability to read and interpret PCB schematics and understand hardware level constraints 
  • Familiarity with embedded software integration and HW/SW boundary definition 
  • Proficiency with AXI protocols, including AXI4 family 
  • Knowledge of common bus interfaces such as SPI, I2C, UART, and similar standards 
  • Demonstrated success operating with ownership in fast paced, collaborative environments 
Additional Responsibilities 
  • Design and support FPGA systems intended for space environments, including consideration of radiation impacts, mitigation strategies, and long duration reliability
  • Must be able to lift up to 50 lbs as required for hardware bring up and lab activities
  • Join a team of best-in-class engineers building the foundation of planetary surface exploration
  • Equity ownership in the company
  • Comprehensive health benefits, including medical, dental, vision, and mental health support
  • 401(k) plan with company match
  • Flexible PTO and parental leave
  • Home office set up reimbursement
  • Fully flexible and remote friendly work environment
  • Weekly lunch stipend, plus complimentary snacks and beverages on-site
  • Once a month social hour on-site with food and drinks

Apply