ZipRecruiter

Log In

1

Internship Asic Rtl Design Engineer Jobs in Ashburn, VA

Trident Systems LLC

Senior FPGA Engineer

Fairfax, VA · On-site

$97K - $181K/yr

Senior FPGA Engineer Requisition ID: 1806 Position Location: Fairfax, VA Position Reports To ... The ideal candidate brings deep expertise in RTL design, timing closure, simulation, and system ...

Logos Technologies, Inc.

Engineer

Fairfax, VA · On-site

... of RTL design for FPGAs in VHDL or Verilog, or System Verilog - knowledge of all 3 strongly ... C++ programming * Mapping data processing algorithms to FPGAs using Vitis HLS * Implementing AI/ML ...

Logos Technologies, Inc.

Engineer

Fairfax, VA · On-site

... of RTL design for FPGAs in VHDL or Verilog, or System Verilog - knowledge of all 3 strongly ... C++ programming * Mapping data processing algorithms to FPGAs using Vitis HLS * Implementing AI/ML ...

Rocket Lab Corporation

Sr. FPGA Engineer II

Chantilly, VA · On-site

$133K - $171K/yr

... ASIC-based image processing algorithms. * Experience in both creating IP from scratch in RTL and ... PCB design and schematic capture and layout with tools such as Altium Designer. * Active TS/SCI ...

Logos Technologies, Inc.

Engineer

Fairfax, VA

... of RTL design for FPGAs in VHDL or Verilog, or System Verilog - knowledge of all 3 strongly ... C++ programming * Mapping data processing algorithms to FPGAs using Vitis HLS * Implementing AI/ML ...

previous pagenext page

Showing results 21-40

All JobsAsic Rtl Design Engineer JobsInternship Asic Rtl Design Engineer JobsInternship Asic Rtl Design Engineer Jobs in Ashburn, VA

Internship Asic Rtl Design Engineer information

See Ashburn, VA salary details

$96.1K

$153.6K

$206.6K

How much do internship asic rtl design engineer jobs pay per year?

As of Aug 22, 2026, the average yearly pay for internship asic rtl design engineer in Ashburn, VA is $153,591.00, according to ZipRecruiter salary data. Most workers in this role earn between $134,500.00 and $184,100.00 per year, depending on experience, location, and employer.

What is an internship ASIC RTL design engineer?

An Internship ASIC RTL (Register Transfer Level) Design Engineer is a student or recent graduate who assists in designing and developing digital integrated circuits (ICs) using hardware description languages like Verilog or VHDL. They work under the guidance of senior engineers to create, simulate, and verify RTL code for ASIC (Application Specific Integrated Circuit) projects. The role provides hands-on experience with the chip design process, including synthesis, timing analysis, and verification. Interns gain valuable exposure to industry-standard tools and methodologies, helping them prepare for a full-time engineering career.

What does an internship ASIC RTL design engineer do?

As an ASIC RTL Design Engineering intern, you'll typically work on tasks such as writing and verifying RTL code using languages like Verilog or VHDL, assisting with simulation and debugging, and collaborating closely with senior engineers on real design blocks. Interns often participate in design reviews, update documentation, and may get hands-on experience with synthesis and timing analysis tools. This role is highly collaborative and provides exposure to the complete ASIC development cycle, making it an excellent opportunity to build foundational skills and gain insight into industry-standard methodologies.

What are the key skills and qualifications needed to thrive as an internship ASIC RTL design engineer?

To thrive as an Internship ASIC RTL Design Engineer, you need a solid understanding of digital logic design, computer architecture, and proficiency in HDL languages like Verilog or VHDL, typically supported by coursework in electrical or computer engineering. Familiarity with industry-standard EDA tools such as Synopsys, Cadence, or Mentor Graphics, and simulation environments is highly valuable. Strong analytical thinking, attention to detail, and effective communication skills help interns collaborate with teams and learn quickly in a fast-paced environment. These skills and qualities are essential for contributing to complex chip design projects and ensuring accuracy and efficiency in RTL development.

What is the difference between Internship Asic Rtl Design Engineer vs Asic Verification Engineer?

AspectInternship Asic Rtl Design EngineerAsic Verification Engineer
CredentialsTypically pursuing or recently completed a degree in Electrical Engineering or Computer EngineeringSimilar educational background, often with additional coursework in verification methodologies
Work EnvironmentInternship setting, supervised, focused on learning and assisting in RTL design tasksFull-time role, focused on testing and verifying RTL designs
Industry UsageUsed in semiconductor and chip design companies during early career stagesCommon in companies developing complex integrated circuits and chips

The Internship Asic Rtl Design Engineer focuses on assisting in RTL design tasks during an internship, emphasizing learning and support. In contrast, the Asic Verification Engineer is responsible for verifying RTL designs to ensure functionality. Both roles require similar educational backgrounds but differ in responsibilities and work environment, with verification roles being more advanced and permanent.

What are the most commonly searched types of Asic Rtl Design Engineer jobs in Ashburn, VA?

The most popular types of Asic Rtl Design Engineer jobs in Ashburn, VA are:

What are popular job titles related to Internship Asic Rtl Design Engineer jobs in Ashburn, VA?

For Internship Asic Rtl Design Engineer jobs in Ashburn, VA, the most frequently searched job titles are:

What job categories do people searching Internship Asic Rtl Design Engineer jobs in Ashburn, VA look for?

The top searched job categories for Internship Asic Rtl Design Engineer jobs in Ashburn, VA are:

What cities near Ashburn, VA are hiring for Internship Asic Rtl Design Engineer jobs?

Cities near Ashburn, VA with the most Internship Asic Rtl Design Engineer job openings:

Internship Asic Rtl Design Engineer jobs near you

Senior FPGA Engineer

Trident Systems LLC

Fairfax, VA • On-site

$97K - $181K/yr

Full-time

Medical, Dental, Vision, Life, Retirement, PTO

This job post has expired today. Applications are no longer accepted.

Job description

Position Title: Senior FPGA Engineer
Requisition ID: 1806
Position Location: Fairfax, VA
Position Reports To: Senior Manager, FPGA Engineering
Supervises Others: No

At Trident Systems Space Electronic Systems (SES) division, we believe in the power of using strong engineering principles to drive innovation and solve complex problems. We foster a culture of rigorous engineering and continuous improvement, leveraging the full knowledge of our organization through collaborative product development processes that include design and peer reviews. We combine our expertise in space electronics with right-sized development processes to create innovative, high-performance space-based electronic systems that meet our customers' evolving needs.

We are a mission partner supporting DoD, Intelligence Community, and Civil space customers. We develop complex, radiation effects mitigated, designs that balance competing requirements in modern space programs, delivering cutting-edge solutions that enable our customers to achieve more in space.

Position Summary

The Senior FPGA Engineer will play a critical role in the design and development of advanced FPGA solutions supporting cutting-edge space-based electronic systems. This position is responsible for architecting, implementing, and verifying complex high-speed programmable logic designs for Software Defined Radios (SDRs), On-Board Processors (OBPs), and storage solutions using the latest AMD (Xilinx) technologies. The ideal candidate brings deep expertise in RTL design, timing closure, simulation, and system integration, and thrives in a collaborative, multi-disciplinary environment delivering mission-critical solutions to DoD, Intelligence Community, and Civil space customers.


Duties and Responsibilities

  • Work within a multi-discipline team of engineers designing Software Defined Radios (SDRs), On-Board Processors (OBPs) and storage solutions for space applications utilizing the latest Xilinx (AMD) technologies (e.g., Zynq Ultrascale+ MPSoC, Zynq Ultrascale+ RFSoC, and Versal ACAP)
  • Create and maintain complete FPGA designs using a combination of VHDL and Vivado IP Integrator with a strong emphasis on efficient data path architecture, reliable timing closures, and high-performance implementations
  • Code, simulate and verify a wide range of RTL modules for FPGAs including modules for digital signal processing (DSP), control algorithms, interfaces to external peripherals, etc.
  • Design and implement solutions that use embedded ARM processors, DDR4 memory, high-speed serial interfaces such as Aurora, JESD204B/C, PCIe, 1G/10G/100G Ethernet, etc.
  • Create and maintain comprehensive simulation test bench modules to ensure a high degree of code coverage and verify functionality of firmware modules
  • Create and maintain Timing Constraints to ensure design is fully constrained and consistent Timing Results are achieved post-implementation
  • Create and maintain IP core level and Top-Level design documents
  • Participate in code reviews, design reviews, and contribute towards FPGA Design methodologies and best practices
  • Work in close collaboration with hardware and software engineers throughout the integration process to ensure that FPGA designs are correctly implemented
  • Mentor junior engineers: provide training, guidance, and support as needed
  • Ability to support travel or off-site work, as needed
  • Perform other duties as assigned

Required Qualifications

  • Bachelor’s degree in Computer Engineering, Electrical Engineering or related technical degree
  • 6+ years of related experience with a bachelor’s degree OR a 4+ years of experience with a master’s degree
  • Experience with firmware design, simulation and verification
  • Thorough understanding of FPGA design methodology including physical synthesis, static timing analysis, place/route, verification, power analysis, and timing closure techniques
  • Experience designing with Xilinx SoC/FPGA devices using the Vivado Design Suite
  • Experience using Vivado IP Integrator
  • Experience with RTL logic design and coding using VHDL
  • Experience writing simulation testbenches to identify bugs and verify designs using SystemVerilog
  • Experience with board bring-up/verification in an electronic lab environment and use of FPGA ILA-based debugging tools such as Vivado HW Debugger, Chipscope, SmartDebug

Preferred Qualifications

  • Experience programming and implementing designs using the Versal AI Engines
  • Experience designing with Microsemi (Microchip) FPGAs using Libero
  • Experience using revision control systems, such as Git
  • Experience using Modelsim/Questasim and/or Aldec simulation tools
  • Experience using simulation verification libraries such as UVVM, UVM, OVM, etc.
  • Familiarity with lab test equipment such as logic analyzers, oscilloscopes, signal generators, spectrum analyzers, etc.
  • Highly productive, self-motivated person able to contribute as an individual and work within a distributed team
  • Digital Signal Processing (DSP)
  • MATLAB and Simulink
  • Linux
  • C/C++

Pay Information

Full-Time Salary Range: $97,000–$181,000

Please note: Actual compensation offered will be determined based on several factors including, but not limited to, relevant experience, skills, education, certifications, internal equity, business considerations, and geographic location where applicable.

Benefits

Hired applicants may be eligible for benefits including but not limited to:

  • Health benefits
  • Medical
  • Dental
  • Vision
  • Basic life with AD&D
  • Short term disability
  • Long term disability
  • Ancillary (Voluntary life with AD&D, accident, critical illness, hospital, and pet)
  • Spending accounts (HSA, FSA, and DCFSA)
  • Paid time off
  • Holidays
  • 401(k) (including company match)
  • Tuition reimbursement
  • Leaves (Parental, maternity, and military)
  • Annual discretionary bonus (for eligible roles)


Trident Systems reserves the right to change or assign other duties to this position.

Trident Systems is an affirmative action and equal opportunity employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, age, sex, national origin, disability status, genetics, protected veteran status, sexual orientation, gender identity or expression, or any other characteristic protected by federal, state or local laws. To request reasonable accommodation to participate in the job application or interview process, please contact recruiting@tridsys.com.

Pay Transparency: The contractor will not discharge or in any other manner discriminate against employees or applicants because they have inquired about, discussed, or disclosed their own pay or the pay of another employee or applicant. However, employees who have access to the compensation information of other employees or applicants as a part of their essential job functions cannot disclose the pay of other employees or applicants to individuals who do not otherwise have access to compensation information, unless the disclosure is (a) in response to a formal complaint or charge, (b) in furtherance of an investigation, proceeding, hearing, or action, including an investigation conducted by the employer, or (c) consistent with the contractor’s legal duty to furnish information. 41 CFR 60-1.35(c)