Cpu Rtl Design Engineer Jobs in Ashburn, VA (NOW HIRING)

... design in RTL (VHDL) and perform module level simulations Perform Synthesis, Place and Route (PAR ... in engineering, engineering technology (chemistry, physics, mathematics, data science, or ...

Bachelor's degree in electrical engineering or equivalent degree, and minimum 4 years of prior ... Execute design (RTL AND/OR HLS (C++ to RTL)) and RTL quality (RDC, CDC, Formal, Lint) * Generate ...

Overview Blue Origin is seeking a Senior FPGA Design and Verification Engineer to develop the ... Strong proficiency in RTL design using VHDL and/or Verilog/SystemVerilog. * Experience implementing ...

... Engineer to join our team in Ashburn, VA. In this senior role, you will lead the design and ... flows including RTL design. This is an onsite position that offers a competitive salary and ...

Principal FPGA Engineer Full Time Employee Full-Time Fairfax, VA, US 3 days ago Requisition ID ... The ideal candidate brings deep expertise in RTL design, timing closure, simulation, and system ...

... of RTL design for FPGAs in VHDL or Verilog, or System Verilog - knowledge of all 3 strongly ... C++ programming * Mapping data processing algorithms to FPGAs using Vitis HLS * Implementing AI/ML ...

Principal FPGA Engineer Requisition ID: 1857 Position Location: Fairfax, VA Position Reports To ... The ideal candidate brings deep expertise in RTL design, timing closure, simulation, and system ...

... of RTL design for FPGAs in VHDL or Verilog, or System Verilog - knowledge of all 3 strongly ... C++ programming * Mapping data processing algorithms to FPGAs using Vitis HLS * Implementing AI/ML ...

... of RTL design for FPGAs in VHDL or Verilog, or System Verilog - knowledge of all 3 strongly ... C++ programming * Mapping data processing algorithms to FPGAs using Vitis HLS * Implementing AI/ML ...

... of RTL design for FPGAs in VHDL or Verilog, or System Verilog - knowledge of all 3 strongly ... C++ programming * Mapping data processing algorithms to FPGAs using Vitis HLS * Implementing AI/ML ...

Principal Engineer - FPGA/ASIC Design Working Pattern: Hybrid (3 office days a week) Working ... Develop RTL utilizing a hardware description language (e.g. VHDL, Verilog, and/or SystemVerilog ...

Principal Engineer - FPGA/ASIC Design Working Pattern: Hybrid (3 office days a week) Working ... Develop RTL utilizing a hardware description language (e.g. VHDL, Verilog, and/or SystemVerilog ...

We are seeking a skilled Senior FPGA Engineer to join our innovative team at Viavi Solutions Inc ... Proficiency in Verilog/SystemVerilog for RTL design. * Experience with industry-standard EDA tools ...

We are seeking a skilled Senior FPGA Engineer to join our innovative team at Viavi Solutions Inc ... Proficiency in Verilog/SystemVerilog for RTL design. * Experience with industry-standard EDA tools ...

... Debug RTL failures in simulation and on hardware targets • Develop constrained-random and ... with design engineers on architecture reviews and interface specifications • Support hardware ...

Mentor junior engineers and provide technical leadership within the digital design team. This ... Proficiency in Verilog/SystemVerilog for RTL design. * Experience with industry-standard EDA tools ...

... FPGA design flow including items such as RTL/gate level simulation, synthesis, place and route ... programmable logic requirements, design documents, and test specifications Proven experience ...

As a FPGA Electrical Engineer - Level 3 or Level 4 located in Dulles, VA, you'll be a linchpin in ... Proficient in FPGA design flow including items such as RTL/gate level simulation, synthesis, place ...

... of RTL design for FPGAs in VHDL or Verilog, or System Verilog - knowledge of all 3 strongly ... C++ programming * Mapping data processing algorithms to FPGAs using Vitis HLS * Implementing AI/ML ...

JR12444**Principal FPGA Engineer - Onsite position**Curtiss-Wright is seeking an experienced ... Strong understanding of FPGA design flow, including RTL design (System Verilog, Verilog, or VHDL ...