Cpu Rtl Design Engineer Jobs in Charlottesville, VA

NRAO Central Development Lab, 1180 Boxwood Estate Rd, CHARLOTTESVILLE, Virginia, United States of America

Position Description:

The National Radio Astronomy Observatory (NRAO) is a prestigious research and development organization that plays a vital role in the study of the universe. Associated Universities, Inc. (AUI) is a nonprofit organization that manages and operates the NRAO under a cooperative agreement with the National Science Foundation. The Observatory is a hub for technological and scientific collaboration, operating state‑of‑the‑art radio telescope facilities for use by the international scientific community. The Observatory has been instrumental in the study of black holes, galaxies, and the early universe.

The Central Development Laboratory (CDL) at the NRAO is seeking an experienced FPGA System Architect to join its digital design team. The engineer will lead the technical execution, integration, and deployment of a digital signal processing system for a next‑generation radio telescope synthesis array, guiding the system through implementation, design reviews, integration, and operational deployment while supporting requirements refinement as needed.

CDL's digital design team develops advanced digital signal processing systems that enable radio astronomy research, supporting scientific studies of galaxy formation, the origins of stars and planets, and black holes.

The selected candidate will lead the technical development and execution of FPGA‑based systems, with an emphasis on high‑throughput digital signal processing, including digitized receiver data acquisition, calibration processing, and frequency channelization. The role combines system‑level technical ownership with hands‑on FPGA development responsibilities, including RTL development and system integration activities as required.

Working within a small, centralized team, the engineer will collaborate across internal groups and provide technical leadership for systems shared with the international scientific community. The role requires strong time management, the ability to manage multiple concurrent efforts, effective cross‑disciplinary communication, and the ability to balance system‑level ownership with hands‑on development responsibilities.

The location for this position will be based at the Central Development Laboratory in Charlottesville, Virginia.

• Lead the architecture, design, integration, and deployment of the antenna‑side FPGA‑based digital signal processing system from ADC input through channelized output
• Lead work package planning, technical scheduling, and execution tracking
• Define subsystem decomposition, interfaces, and data flow across FPGA processing elements, embedded software, timing and synchronization systems, digitizers, and external data transport systems
• Execute subsystem development against system requirements and support requirements refinement and change requests during system development
• Define and evaluate implementation tradeoffs involving FPGA resource utilization, latency, throughput, timing margins, and implementation complexity
• Define and guide implementation of FPGA‑based processing functions, including receiver calibration and frequency channelization
• Contribute to FPGA implementation activities including RTL development, verification, timing analysis, and system integration, as required
• Lead subsystem design reviews and contribute to system‑level design reviews
• Coordinate technical activities across FPGA, embedded software, and related engineering efforts within the work package
• Provide technical direction and task coordination for engineering staff and external collaborators
• Document system architectures, interfaces, design decisions, and verification approaches clearly

Work is mission driven, team oriented and typically performed in an office setting within a research or development environment.

• Bachelor's degree in Electrical Engineering or related field
• Eight years of experience developing complex FPGA‑based digital signal processing systems
• Experience leading the architecture, development, integration, and deployment of FPGA‑based systems
• Experience defining system architectures, subsystem interfaces, and data flows across FPGA processing, embedded software, and external system interfaces
• Experience with high‑throughput DSP systems, including digitized signal acquisition, calibration processing, and channelization
• Experience leading technical teams, coordinating multi‑disciplinary efforts, and leading subsystem design reviews
• Experience with timing and synchronization concepts for high‑throughput FPGA systems
• Solid understanding of digital design fundamentals and FPGA development flows, including synthesis, timing analysis, place‑and‑route, and system integration
• Hands‑on experience with RTL development using hardware description languages
• Experience with high‑speed interfaces and data transport technologies relevant to FPGA systems

• Experience defining and executing FPGA verification and validation approaches, including simulation, system integration, and end‑to‑end testing
• Experience with RF‑series FPGA devices with integrated ADC capability or similar direct digitization platforms
• Experience with radio astronomy, software‑defined radio, or high‑performance signal processing systems
• Experience with receiver calibration techniques and frequency channelization implementations
• Familiarity with version control tools and collaborative development workflows
• Experience with Linux‑based embedded environments and hardware/software integration
• Familiarity with mechanical, thermal, and SWaP (size, weight, and power) considerations for FPGA‑based systems and deployment environments

• Strong written and verbal communication skills with demonstrated ability to coordinate technical efforts across multiple teams
• Strong leadership ability
• Attention to detail is critical

Observatory employees must be authorized to work in the United States. The Observatory presently cannot sponsor H-1B Visas for this position.

The starting salary of this position is between $90,015-$126,000. Factors which may affect starting pay within this range may include: education, experience, skills, competencies, other qualifications of the successful candidate, as well as internal equity and labor market conditions.

Associated Universities, Inc (AUI) offers a comprehensive benefits package addressing the needs of employees and their families with most benefits beginning on the first day of employment, subject to eligibility requirements. AUI provides:

• Excellent paid time off (13 holidays, annual accrual of up to 24 vacation days)
• Medical, dental and vision plans are effective on the first day of employment.
• AUI’s retirement benefit contributes an amount equal to 10 percent of a qualified participant’s base pay with no required employee contribution.

AUI is an equal opportunity employer. To view our complete statement, please visit https://public.nrao.edu/careers/. If you require reasonable accommodation for any part of the application or hiring process, you may submit your request by sending an email to resumes@nrao.edu. PM20