ZipRecruiter

Log In

1

Internship Analog Layout Jobs (NOW HIRING)

Qualcomm

RF/Analog IC Design Engineer

Santa Clara, CA · On-site

D. in Electrical Engineering with internship or publication. • 3+ years of experience in one or ... with layout engineers under minimal guidance to generate the layout of circuits and conduct ...

Marvell

Staff Engineer, Analog IC Design

Irvine, CA · On-site

$216K/yr

Supervising Analog Custom Layout Experience in measuring IC performance and debug of design to ... every stage - from internship to retirement and through life's most important moments. Our ...

next page

Showing results 1-20

People also search for

All JobsAnalog Layout JobsInternship Analog Layout Jobs

Internship Analog Layout information

See salary details

$77K

$186.2K

$203K

How much do internship analog layout jobs pay per year?

As of Jun 5, 2026, the average yearly pay for internship analog layout in the United States is $186,238.00, according to ZipRecruiter salary data. Most workers in this role earn between $202,000.00 and $202,000.00 per year, depending on experience, location, and employer.

What are the key skills and qualifications needed to thrive as an Analog Layout Intern, and why are they important?

To thrive as an Analog Layout Intern, you need a solid understanding of semiconductor fundamentals, circuit design principles, and a relevant educational background in electrical engineering or a related field. Familiarity with CAD tools such as Cadence Virtuoso and knowledge of industry standards like DRC/LVS checks are typically required. Attention to detail, strong problem-solving skills, and effective communication set outstanding candidates apart. These skills ensure accurate circuit layouts, efficient teamwork, and the ability to meet stringent design specifications crucial in the semiconductor industry.

What types of projects and responsibilities can I expect during an Analog Layout Internship?

As an Analog Layout Intern, you can expect to work on tasks such as drafting and optimizing circuit layouts using EDA tools, assisting with layout verification (DRC/LVS), and collaborating closely with senior layout engineers and circuit designers. Interns often contribute to real project blocks under supervision, gaining hands-on experience in matching, parasitic extraction, and design rule compliance. This role provides the opportunity to learn industry standards, participate in design reviews, and build a strong foundation for future full-time roles in analog or mixed-signal IC design.

What is an Internship Analog Layout?

An Internship Analog Layout is a temporary position for students or recent graduates who assist in the design and layout of analog integrated circuits within a semiconductor or electronics company. Interns in this role work closely with experienced engineers to create precise circuit layouts, optimize chip area, and ensure electrical performance. They learn to use Electronic Design Automation (EDA) tools and follow industry standards for layout practices. This internship provides hands-on experience in the field of analog IC design, often as part of a university degree program.

What is the difference between Internship Analog Layout vs Analog IC Design Engineer?

AspectInternship Analog LayoutAnalog IC Design Engineer
Required CredentialsTypically pursuing or recently completed electrical engineering or related degreeBachelor's or Master's in Electrical Engineering or related field, with experience in analog design
Work EnvironmentInternship setting, often in a semiconductor or electronics company, focusing on layout tasksFull-time professional role, involved in designing, simulating, and testing analog circuits
Employer & Industry UsageUsed in semiconductor companies, research labs, and startups for training and entry-level tasksUsed in established electronics and semiconductor companies for product development

Internship Analog Layout focuses on learning and assisting with the physical placement and routing of analog circuits, often as part of a training program. In contrast, an Analog IC Design Engineer is responsible for designing, analyzing, and optimizing analog integrated circuits, requiring more experience and expertise. Both roles are essential in the semiconductor industry but differ in scope, responsibility, and experience level.

More about Internship Analog Layout jobs
What cities are hiring for Internship Analog Layout jobs? Cities with the most Internship Analog Layout job openings:
What are the most commonly searched types of Analog Layout jobs? The most popular types of Analog Layout jobs are:
What states have the most Internship Analog Layout jobs? States with the most job openings for Internship Analog Layout jobs include:
What job categories do people searching Internship Analog Layout jobs look for? The top searched job categories for Internship Analog Layout jobs are:
Internship Analog Layout jobs near you
Infographic showing various Internship Analog Layout job openings in the United States as of May 2026, with employment types broken down into 17% Internship, and 83% Full Time. Highlights an 100% In-person job distribution, with an average salary of $186,238 per year, or $89.5 per hour.
Principal Engineer, Analog IC Design

Principal Engineer, Analog IC Design

Marvell

Santa Clara, CA

Full-time

Life, Retirement

Posted 24 days ago

Job description

About Marvell

Marvell's semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities.

At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.

Your Team, Your Impact

CE-AMS - Join a world-class analog design team providing high performance analog and mixed mode circuits for industry-leading Networking products. Candidate will have opportunity to architect and design circuits for high performance transceivers and other critical analog functions.

What You Can Expect

  • Analog circuit design, such as PLL, Data Converters, Oscillators and high-speed SerDes blocks (CTLE, FFE, DFE, CDR, PLL, Line driver, etc.) New technique development for next generation SERDES

  • Project leading and management

  • Analog layouts supervise with advanced process node

  • System verification and circuit design spec creation

  • Silicon bring-up, debug and support

  • Team communication and documentation

What We're Looking For

Master's degree and/or PhD Preferred in Electrical Engineering or related fields with 6+ years of experience.

  • Should have strong analog design fundamentals and experience in designing analog circuit blocks such as PLL, Data Converters, Oscillators and high-speed SerDes blocks (CTLE, FFE, DFE, CDR, PLL, Line driver, etc.).

  • Experience with analog design and verification tools (Virtuoso, Spectre, ADE and post layout extraction tools) is a must

  • Knowledge of the fundamentals on signal integrity improvement, noise reduction and Multi-GHz low-jitter clock generation & distribution.

  • Good understanding of analog layouts in FinFet and its effect on high-speed designs

  • Experienced in system level pre-tape out analog validation

  • Experienced in lab chip bring-up and debugging efforts

  • Strongcommunicationanddocumentationskills

  • Technical management experience is a plus

Expected Base Pay Range (USD)

174,530 - 261,400, $ per annum

The successful candidate's starting base pay will be determined based on job-related skills, experience, qualifications, work location and market conditions. The expected base pay range for this role may be modified based on market conditions.

Additional Compensation and Benefit Elements

Marvell is committed to providing exceptional, comprehensive benefits that support our employees at every stage - from internship to retirement and through life's most important moments. Our offerings are built around four key pillars: financial well-being, family support, mental and physical health, and recognition. Highlights include an employee stock purchase plan with a 2-year look back, family support programs to help balance work and home life, robust mental health resources to prioritize emotional well-being, and a recognition and service awards to celebrate contributions and milestones. We look forward to sharing more with you during the interview process.

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.

Any applicant who requires a reasonable accommodation during the selection process should contact Marvell HR Helpdesk at TAOps@marvell.com.

Interview Integrity

To support fair and authentic hiring practices, candidates are not permitted to use AI tools (such as transcription apps, real-time answer generators like ChatGPT or Copilot, or automated note-taking bots) during interviews.

These tools must not be used to record, assist with, or enhance responses in any way. Our interviews are designed to evaluate your individual experience, thought process, and communication skills in real time. Use of AI tools without prior instruction from the interviewer will result in disqualification from the hiring process.

This position may require access to technology and/or software subject to U.S. export control laws and regulations, including the Export Administration Regulations (EAR). As such, applicants must be eligible to access export-controlled information as defined under applicable law. Marvell may be required to obtain export licensing approval from the U.S. Department of Commerce and/or the U.S. Department of State. Except for U.S. citizens, lawful permanent residents, or protected individuals as defined by 8 U.S.C. 1324b(a)(3), all applicants may be subject to an export license review process prior to employment.

#LI-TD1

Apply