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Ic Layout Mask Designer Jobs in California (NOW HIRING)

Neuralink

Analog IC Layout Engineer

South San Francisco, CA · On-site

$83K - $139K/yr

You will have the opportunity to collaborate closely with chip designers, electrical engineers ... Physical verification of custom IC mask layouts (LVS, DRC, ERC) Required Qualifications: * Bachelor ...

Neuralink

Analog IC Layout Engineer

South San Francisco, CA · On-site

$83K - $139K/yr

You will have the opportunity to collaborate closely with chip designers, electrical engineers ... Physical verification of custom IC mask layouts (LVS, DRC, ERC) Required Qualifications: * Bachelor ...

SpaceX

RFIC Layout Designer (RFIC Engineering)

Irvine, CA · On-site

$120K - $170K/yr

You will be an integral part of the IC design team and lead the discipline of layout at the technical level, and will work with RFIC/mixed signal designers on full chip layout of custom analog and ...

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Ic Layout Mask Designer information

What does an IC Layout Mask Designer do?

An IC Layout Mask Designer creates the physical design of integrated circuits (ICs) by translating circuit schematics into precise geometric patterns. These patterns are used to fabricate semiconductor chips via photolithography. The role involves ensuring circuit performance, optimizing layouts for electrical and manufacturability requirements, and working closely with design and fabrication teams. Proficiency in EDA tools, design rules, and CMOS technology is essential.

What are the key skills and qualifications needed to thrive as an IC Layout Mask Designer?

To thrive as an IC Layout Mask Designer, you need a solid background in semiconductor physics, electronic circuit design, and proficiency with CAD tools such as Cadence Virtuoso or Mentor Graphics. Experience with industry-standard IC layout design and verification tools, as well as knowledge of relevant process design rules, is highly valued. Strong attention to detail, problem-solving capabilities, and the ability to collaborate across multidisciplinary teams are key soft skills for this role. These competencies are essential to ensure accuracy, manufacturability, and performance in complex integrated circuit designs.

What are some common challenges faced by IC Layout Mask Designers in their daily work?

IC Layout Mask Designers often face challenges such as managing complex design constraints, optimizing layouts for manufacturability, and ensuring strict adherence to foundry design rules. Balancing performance, area, and power requirements while coordinating closely with circuit and verification engineers can add to the complexity. Staying updated with evolving semiconductor processes and continually learning new layout techniques are also important aspects of the role. Despite these challenges, many designers find the work rewarding due to the impact their contributions have on innovative electronics products.

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Ic Layout Mask Designer jobs near you
Infographic showing various Ic Layout Mask Designer job openings in California as of August 2026, with employment types broken down into 85% Full Time, 11% Part Time, 2% Contract, and 2% Nights. Highlights an 93% Physical, 3% Hybrid, and 4% Remote job distribution.

Analog IC Layout Engineer

Neuralink

South San Francisco, CA • On-site

Full-time

Re-posted 20 days ago

Job description

Team Description:

The Brain Interfaces Soc Department delivers chip architecture and silicon implementation of neural recording and stimulation system-on-chip (SoC) for high-bandwidth brain-computer interfaces. We have crafted a team of exceptional engineers whose mission is to push the frontiers of what is possible today and define the future.

Job Description and Responsibilities:

We are looking for experienced and hands-on engineers with a creative and initiative mindset, who are interested in exploring the next-generation chip design with advanced architectures and hardware accelerators with a goal of enhancing the energy efficiency, information entropy, and scalability of our wireless brain-computer interfaces towards the physical limit of silicon technology. The ideal candidates are energetic people who get excited about building things, are highly analytical, and enjoy tackling new problems. You will have the opportunity to collaborate closely with chip designers, electrical engineers, algorithms engineers, and software engineers on a small, agile team. As an Analog IC Layout Engineer, your responsibilities will include:

  • Crafting state-of-the-art layouts for mixed-signal and analog circuits
    • Amplifiers
    • Filters
    • Switched capacitor circuits
    • Oscillators
    • Data converters
    • Power management circuits
  • Reviewing layout floorplans and analyzing high-fidelity circuits with circuit engineers
  • Physical verification of custom IC mask layouts (LVS, DRC, ERC)

Required Qualifications:

  • Bachelor of Science in Computer Engineering or related field
  • 2+ years of experience in analog and mixed-signal IC layout design
  • 1+ year experience with FinFET technologies
  • Ability to identify the best approach to solving problems

Preferred Qualifications:

  • Programming/scripting knowledge in SKILL, TCL, Shell, C/C++, and/or Python
  • Proven expertise in implementing analog and mixed-signal layout designs, achieving tight matching, low noise, and low power consumption
  • Understanding on failure-prone circuit and layout structures
  • Experience with analog DFM standards
  • Experience with layout P-cell design and implementation
  • Experience with layout automation 

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