Mountain View, CA · On-site
$236K/yr
You'll create high-quality, manufacturable analog layouts, collaborate with design engineers, and ensure designs meet electrical and DRC/LVS requirements. Requirements: Proven analog IC layout ...
Mountain View, CA · On-site
$236K/yr
You'll create high-quality, manufacturable analog layouts, collaborate with design engineers, and ensure designs meet electrical and DRC/LVS requirements. Requirements: Proven analog IC layout ...
San Jose, CA · On-site
$210K - $305K/yr
Your Impact As a Package Layout Team Leader, you will lead and grow the San Jose layout team while supporting the execution of complex package programs. You will provide technical guidance ...
San Jose, CA · On-site
$210K - $305K/yr
Your Impact As a Package Layout Team Leader, you will lead and grow the San Jose layout team while supporting the execution of complex package programs. You will provide technical guidance ...
Milpitas, CA · On-site
Lead full-custom IC layout design and verification, including chip floor planning, analog IP layout ... Co-work with designers on block level and top-level floor planning * Layout review for power/gnd ...
Milpitas, CA · On-site
Lead full-custom IC layout design and verification, including chip floor planning, analog IP layout ... Co-work with designers on block level and top-level floor planning * Layout review for power/gnd ...
Santa Clara, CA · On-site
$156K - $160K/yr
Collaborating with other column ADC designers to optimize column ADC's performance with minimum ... Responsible for full-custom analog IC layout and physical verification (DRC/ANT/DFM/ERC/LVS) using ...
Santa Clara, CA · On-site
$156K - $160K/yr
Collaborating with other column ADC designers to optimize column ADC's performance with minimum ... Responsible for full-custom analog IC layout and physical verification (DRC/ANT/DFM/ERC/LVS) using ...
Santa Clara, CA · On-site
$156K - $160K/yr
Collaborating with other column ADC designers to optimize column ADC's performance with minimum ... Responsible for full-custom analog IC layout and physical verification (DRC/ANT/DFM/ERC/LVS) using ...
Santa Clara, CA · On-site
$156K - $160K/yr
Collaborating with other column ADC designers to optimize column ADC's performance with minimum ... Responsible for full-custom analog IC layout and physical verification (DRC/ANT/DFM/ERC/LVS) using ...
Collaborating with other column ADC designers to optimize column ADC's performance with minimum ... Responsible for full-custom analog IC layout and physical verification (DRC/ANT/DFM/ERC/LVS) using ...
Quick apply
Collaborating with other column ADC designers to optimize column ADC's performance with minimum ... Responsible for full-custom analog IC layout and physical verification (DRC/ANT/DFM/ERC/LVS) using ...
Santa Clara, CA · On-site
$156K - $160K/yr
Collaborating with other column ADC designers to optimize column ADC's performance with minimum ... Responsible for full-custom analog IC layout and physical verification (DRC/ANT/DFM/ERC/LVS) using ...
Santa Clara, CA · On-site
$156K - $160K/yr
Collaborating with other column ADC designers to optimize column ADC's performance with minimum ... Responsible for full-custom analog IC layout and physical verification (DRC/ANT/DFM/ERC/LVS) using ...
Santa Clara, CA · On-site
$148K - $203K/yr
Responsibilities include user support for Behavioral, RTL and Analog Designs, Schematics, Analog Mixed-Signal Simulations, IC Physical Design layout, CAD tool customizations, Linux Support ...
Quick apply
Santa Clara, CA · On-site
$148K - $203K/yr
Responsibilities include user support for Behavioral, RTL and Analog Designs, Schematics, Analog Mixed-Signal Simulations, IC Physical Design layout, CAD tool customizations, Linux Support ...
Santa Clara, CA · On-site
$232 - $368/hr
Own end-to-end PIC product delivery: architecture, design, layout, DRC/LVS verification, tapeout ... Mentor and technically guide a team of photonics designers; set technical direction for the ...
Santa Clara, CA · On-site
$232 - $368/hr
Own end-to-end PIC product delivery: architecture, design, layout, DRC/LVS verification, tapeout ... Mentor and technically guide a team of photonics designers; set technical direction for the ...
Own end-to-end PIC product delivery: architecture, design, layout, DRC/LVS verification, tapeout ... Mentor and technically guide a team of photonics designers; set technical direction for the ...
Own end-to-end PIC product delivery: architecture, design, layout, DRC/LVS verification, tapeout ... Mentor and technically guide a team of photonics designers; set technical direction for the ...
Own end-to-end PIC product delivery: architecture, design, layout, DRC/LVS verification, tapeout ... Mentor and technically guide a team of photonics designers; set technical direction for the ...
Own end-to-end PIC product delivery: architecture, design, layout, DRC/LVS verification, tapeout ... Mentor and technically guide a team of photonics designers; set technical direction for the ...
... IC codesign. * Familiarity with layout tools (e.g., Expedition Package Designer, Pads Layout ... Altium, etc.). * Experience with layout tool scripting languages (e.g., SKILL or Python) to enable ...
New
... IC codesign. * Familiarity with layout tools (e.g., Expedition Package Designer, Pads Layout ... Altium, etc.). * Experience with layout tool scripting languages (e.g., SKILL or Python) to enable ...
New
Cupertino, CA · On-site
Drive mask design to implement layout view of designs. Top-level simulations to validate top-level ... it applies to analog IC designs Proven working experience in using spectrum analyzers ...
Cupertino, CA · On-site
Drive mask design to implement layout view of designs. Top-level simulations to validate top-level ... it applies to analog IC designs Proven working experience in using spectrum analyzers ...
Cupertino, CA · On-site
Drive mask design to implement layout view of designs. Top-level simulations to validate top-level ... it applies to analog IC designs Proven working experience in using spectrum analyzers ...
Cupertino, CA · On-site
Drive mask design to implement layout view of designs. Top-level simulations to validate top-level ... it applies to analog IC designs Proven working experience in using spectrum analyzers ...
Cupertino, CA · On-site
Drive mask design to implement layout view of designs. Top-level simulations to validate top-level ... it applies to analog IC designs Proven working experience in using spectrum analyzers ...
Cupertino, CA · On-site
Drive mask design to implement layout view of designs. Top-level simulations to validate top-level ... it applies to analog IC designs Proven working experience in using spectrum analyzers ...
Cupertino, CA · On-site
Drive mask design to implement layout view of designs. Top-level simulations to validate top-level ... it applies to analog IC designs Proven working experience in using spectrum analyzers ...
Cupertino, CA · On-site
Drive mask design to implement layout view of designs. Top-level simulations to validate top-level ... it applies to analog IC designs Proven working experience in using spectrum analyzers ...
Cupertino, CA · On-site
Drive mask design to implement layout view of designs. Top-level simulations to validate top-level ... it applies to analog IC designs Proven working experience in using spectrum analyzers ...
Cupertino, CA · On-site
Drive mask design to implement layout view of designs. Top-level simulations to validate top-level ... it applies to analog IC designs Proven working experience in using spectrum analyzers ...
Cupertino, CA · On-site
Drive mask design to implement layout view of designs. Top-level simulations to validate top-level ... it applies to analog IC designs Proven working experience in using spectrum analyzers ...
Cupertino, CA · On-site
Drive mask design to implement layout view of designs. Top-level simulations to validate top-level ... it applies to analog IC designs Proven working experience in using spectrum analyzers ...
Conduct full-custom IC layout or direct layout engineers, ensuring DRC/LVS-clean designs at mmWave frequencies. * Perform post-layout extraction and EM simulation (Ansys HFSS, EMX, ADS Momentum) to ...
Quick apply
Conduct full-custom IC layout or direct layout engineers, ensuring DRC/LVS-clean designs at mmWave frequencies. * Perform post-layout extraction and EM simulation (Ansys HFSS, EMX, ADS Momentum) to ...
Role Overview We are seeking a highly experienced Senior or Staff Analog/Mixed-Signal IC Designer ... with layout engineers to meet stringent PPA targets. * Drive pre-silicon simulation and post ...
Quick apply
Role Overview We are seeking a highly experienced Senior or Staff Analog/Mixed-Signal IC Designer ... with layout engineers to meet stringent PPA targets. * Drive pre-silicon simulation and post ...
$16.57 is the 25th percentile. Wages below this are outliers.
$9.96 - $18.12
31% of jobs
$18.12 - $26.27
16% of jobs
The median wage is $28.71 / hr.
$26.27 - $34.42
11% of jobs
$34.42 - $42.57
15% of jobs
$47.67 is the 75th percentile. Wages above this are outliers.
$42.57 - $50.73
4% of jobs
$50.73 - $58.88
6% of jobs
$58.88 - $67.03
5% of jobs
$67.03 - $75.18
3% of jobs
$75.18 - $83.33
2% of jobs
$83.33 - $91.49
3% of jobs
$91.49 - $99.64
3% of jobs
$9
$40
$99
An IC Layout Designer is responsible for creating the physical design of integrated circuits (ICs) based on schematics provided by circuit designers. They use specialized software tools to arrange transistors, resistors, capacitors, and interconnections while ensuring proper functionality, manufacturability, and performance. Their role involves optimizing layouts for power, area, and signal integrity while adhering to design rules and foundry guidelines. IC Layout Designers work closely with circuit designers and verification engineers to meet project specifications and ensure successful chip fabrication.
As an IC Layout Designer, your typical day involves interpreting circuit schematics, translating them into physical layouts using specialized EDA tools, and running verification checks to ensure compliance with design and manufacturing rules. You will collaborate closely with circuit designers and verification engineers to address layout-related challenges and optimize designs for performance, area, and yield. Regular communication and feedback sessions are common, as is updating documentation and maintaining clear records of design changes. These tasks help ensure project timelines are met and high-quality integrated circuits are delivered.
To thrive as an IC Layout Designer, you need a strong background in semiconductor physics, circuit design principles, and experience with industry-standard layout tools such as Cadence Virtuoso or Synopsys Custom Compiler, often supported by a degree in Electrical Engineering or a related field. Familiarity with DRC/LVS verification, PDKs, and EDA tools, as well as knowledge of relevant process nodes, is essential. Attention to detail, effective teamwork, and strong communication skills enable designers to collaborate with circuit engineers and deliver precise layouts under tight deadlines. These competencies ensure the creation of optimized, reliable integrated circuits while meeting stringent performance and manufacturability requirements.
The most popular types of Ic Layout Designer jobs in California are:
For Ic Layout Designer jobs in California, the most frequently searched job titles are:
The top searched job categories for Ic Layout Designer jobs in California are:
Cities in California with the most Ic Layout Designer job openings:
$236K/yr
Other
Posted 9 days ago
Job Title: Analog Layout Engineer – Contract (TSMC N3)
Location: Mountain View, CA – Onsite
Contract: 6 Months
Onsite Requirement: Candidates must be able to work onsite in Mountain View at least 4 days per week. During tapeout periods, engineers will be required onsite 5 days per week, with potential weekend support.
Sourced by ZipRecruiter
It services
1 - 10 Employees
Los Angeles, CA, US
2012
