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Ic Layout Design Engineer Jobs in Massachusetts (NOW HIRING)

Lightmatter

Analog IC Design Engineer, AMS

Boston, MA · On-site

$190K - $230K/yr

Run post-layout and mixed-signal top-level simulations to validate integration * Define production ... IC is a plus * Experience in chip top-level design is a plus #LI-FM1 We offer competitive ...

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Ic Layout Design Engineer information

See Massachusetts salary details

$49.1K

$132K

$202.6K

How much do ic layout design engineer jobs pay per year?

As of Aug 7, 2026, the average yearly pay for ic layout design engineer in Massachusetts is $131,982.00, according to ZipRecruiter salary data. Most workers in this role earn between $98,300.00 and $157,300.00 per year, depending on experience, location, and employer.

What does an IC layout design engineer do?

An IC Layout Design Engineer is responsible for creating the physical design of integrated circuits (ICs) based on schematic designs. They ensure optimal placement and routing of transistors and interconnections while meeting performance, power, and area constraints. They work closely with circuit designers and verification engineers to ensure manufacturability and compliance with design rules. Tools like Cadence Virtuoso or Mentor Graphics are commonly used in this role.

What are the key skills and qualifications needed to thrive as an IC layout design engineer?

To thrive as an IC Layout Design Engineer, you need strong expertise in analog and/or digital IC layout, semiconductor device physics, and an educational background in electrical engineering or a related field. Familiarity with industry-standard EDA tools such as Cadence Virtuoso, Mentor Graphics, and proficiency with layout verification techniques (like DRC and LVS) are typically required. Exceptional attention to detail, effective communication, and the ability to collaborate closely with circuit design teams are valuable soft skills. These skills are essential to ensure the successful design, optimization, and integration of complex integrated circuits in high-performance environments.

What are the common challenges faced by IC layout design engineers on the job?

IC Layout Design Engineers often encounter challenges such as meeting strict design specification requirements, managing complex circuitry within limited silicon area, and ensuring layouts comply with manufacturing constraints. They may need to troubleshoot and resolve issues with DRC/LVS errors, work under tight project deadlines, and adapt quickly to changes in design parameters. Close collaboration with circuit design engineers and verification teams is common, requiring strong teamwork and effective communication. These challenges make the role dynamic and can provide excellent opportunities to develop specialized skills and advance into lead or principal engineering positions over time.

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Ic Layout Design Engineer jobs near you
Infographic showing various Ic Layout Design Engineer job openings in Massachusetts as of August 2026, with employment types broken down into 87% Full Time, 8% Part Time, and 5% Contract. Highlights an 85% Physical, 4% Hybrid, and 11% Remote job distribution, with an average salary of $131,982 per year, or $63.5 per hour.

Senior IC Layout Designer (Remote - USA)

Encore Semi, Inc.

Boston, MA • Remote

$65 - $80/hr

Full-time

Medical, Dental, Vision, Life, Retirement, PTO

Posted 13 days ago

Job description

Senior IC Layout Designer (Remote – USA)
Employment Type: Full-Time (Hourly) | Contractor Opportunities Available
Compensation: Competitive Hourly Rate + Benefits + Bonus Opportunities
Work Authorization: US Citizen or Lawful Permanent Resident
Location: 100% Remote (Anywhere in the USA)
Build Next-Generation Silicon at Advanced Technology Nodes
We are looking for a Senior IC Layout Designer to join a highly skilled semiconductor engineering team developing advanced digital and mixed-signal integrated circuits. This role is ideal for an experienced layout professional who enjoys solving complex physical design challenges and turning innovative circuit designs into high-quality, production-ready silicon.
You will work closely with IC designers, verification engineers, and process teams to deliver layouts optimized for performance, power, area, reliability, and manufacturability across advanced process technologies.
What You’ll Do
  • Develop block-level and full-chip physical layouts for complex digital and mixed-signal IC designs.
  • Translate schematics into high-quality layout implementations while maintaining design intent.
  • Perform floorplanning, placement, routing, optimization, and layout refinement for PPA (Power, Performance, Area).
  • Drive DRC, LVS, and ERC closure, including debugging complex layout and verification issues.
  • Analyze and optimize layouts for parasitics, signal integrity, timing, and manufacturability.
  • Collaborate with circuit designers, physical verification teams, and foundry partners during tapeout and silicon release activities.
  • Support improvements in layout methodologies, automation, and design flows.
  • Mentor junior layout engineers and contribute technical expertise across the team.
What You Bring
  • 7+ years of hands-on IC layout design experience in advanced semiconductor technologies.
  • Strong expertise with industry-standard EDA tools such as Cadence Virtuoso, Synopsys tools, or equivalent platforms.
  • Deep understanding of CMOS process technology, physical design concepts, and layout best practices.
  • Proven experience achieving DRC/LVS closure and resolving complex physical verification challenges.
  • Strong knowledge of parasitic extraction, signal integrity, timing impact, and layout optimization techniques.
  • Experience collaborating within cross-functional semiconductor design teams.
Preferred Experience
  • Hands-on experience with FinFET and sub-7nm technology nodes.
  • Experience with high-speed digital, mixed-signal, or advanced SoC designs.
  • Familiarity with layout automation and scripting using SKILL, Python, TCL, or similar languages.
  • Track record supporting successful production tapeouts.
Why Join Us
Join a team working on challenging semiconductor designs where your layout expertise directly impacts silicon performance and product success. You’ll collaborate with experienced engineers tackling real-world challenges in advanced IC development.
If you are passionate about precision layout design, advanced nodes, and building world-class silicon, we would love to connect.
We offer a competitive hourly rate ranging from $65 to $80 per hour, based on experience, skills, and qualifications. The position includes a comprehensive benefits package and bonus opportunities
Full-Time Benefits:
• 15 days of PTO per calendar year
• 10 paid Holidays per calendar year
• Comprehensive Medical Benefits: Company covers 80% of premiums for Employee and Dependents
• Dental & Vision: Company covers 50% of premiums for Employee and Dependents
• Voluntary Benefits: Life Insurance, FSA (Health and Dependent, Limited Purpose), HAS, and Gap Insurance
• Employee Assistant Program (EAP)
• 401k - Traditional & Roth
• Life/AD&D and Long-Term Disability
• Tuition reimbursement
Equal Opportunity Policy Statement
Encore Semi, Inc. is an Equal Opportunity Employer that does not discriminate on the basis of actual or perceived race, religion, creed, color, age, sex, sexual orientation, gender, gender identity or expression, national origin, genetics, ancestry, marital status, civil union status, medical condition, disability (mental and physical), military and veteran status, pregnancy, childbirth and related medical conditions, or any other characteristic protected by applicable federal, state, or local laws and ordinances.
Encore Semi is also committed to compliance with all fair employment practices regarding citizenship and immigration status.
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