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High Speed Adc Design Engineer Jobs (NOW HIRING)

NY · On-site

$62K - $85K/yr

The Role Amphenol Military High-Speed is seeking a Design Engineer to work out of it's facility in Sidney, NY. The key responsibilities of this Design Engineer include, but are not limited to:

TI's Precision ADC (PADC) team develops industry leading 24-bit high precision ADCs and Sensing AFE ... Analog circuit designs involving high speed, high precision, low noise, low power * Top-level and ...

FPGA System Design Engineer

San Jose, CA · On-site

$144K - $198K/yr

FPGA System Design Engineer** to join our Aerospace, Defense, and Government (ADG) solutions team ... Learning + High-speed ADC/DAC architectures + RF and Software Defined Radio (SDR) systems*

TI's Precision ADC (PADC) team develops industry leading 24-bit high precision ADCs and Sensing AFE ... Analog circuit designs involving high speed, high precision, low noise, low power * Top-level and ...

$90K - $125K/yr

FPGA System Design Engineer** to join our Aerospace, Defense, and Government (ADG) solutions team ... Learning + High-speed ADC/DAC architectures + RF and Software Defined Radio (SDR) systems*

D. in Electrical Engineering, Physics or Solid State Physics, including new graduates through ... ADC). * Solid expertise with EDA CAD tools, custom analog layout, 3D EM modeling * Experience in ...

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Infographic showing various High Speed Adc Design Engineer job openings in the United States as of August 2026, with employment types broken down into 1% As Needed, 80% Full Time, 16% Part Time, and 3% Contract. Highlights an 90% Physical, 1% Hybrid, and 9% Remote job distribution.

Principal Analog IC Design Engineer, High Speed SerDes

San Jose, CA • On-site

Cadence Design Systems, Inc.
Software Development • 5 - 10K employees

$136K - $253K/yr

Full-time

Medical, Dental, Vision, Retirement, PTO

Re-posted 14 days ago


Cadence Design Systems rating

9.0

Company rating: 9.0 out of 10

Based on 5 frontline employees who took The Breakroom Quiz

34th of 247 rated software companies


Job description

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
The Principal Analog IC Designer is responsible for the design and development of analog/mixed signal IC circuit blocks from initial concept/specification through final verification of conformance to customer specifications.
  • Candidate's background should include a minimum of 7 years of experience in CMOS SerDes or high-speed I/O IC design and development.
  • Working knowledge of a set of common SerDes standards and their electrical requirements is a plus.
  • Must have a thorough understanding of jitter and signal equalization techniques
  • Proficient design experience in most of the following SerDes circuit blocks: Driver; Receiver; Serializer; Deserializer; Phase Interpolator; Low jitter PLL; High Speed Clock Distribution; ADC and DAC; Bias and Bandgap; and Voltage Regulators
  • Excellent problem solving skills, analog aptitude, good communication skills, and ability to work cooperatively in a team environment
  • Position requires proficiency in using CAD tools for circuit simulation, layout, and physical verification
  • Cadence tool experience, lab test experience, and design experience at >10Gbps and in <28nm technologies are a plus
  • MS or PhD in EE

The annual salary range for California is $136,500 to $253,500. You may also be eligible to receive incentive compensation: bonus, equity, and benefits. Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure. Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies and work location. Our benefits programs include: paid vacation and paid holidays, 401(k) plan with employer match, employee stock purchase plan, a variety of medical, dental and vision plan options, and more.
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