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Google Ic Design Jobs (NOW HIRING)

Formlabs

Manager, Google Ads

Somerville, MA

Together, we're helping everyone design, prototype, and manufacture faster than ever before. We're ... This is an IC role for someone who's equal parts strategic and operational, and who lets data drive ...

Tessera Labs

Design Engineer

New York, NY · On-site

$179K - $250K/yr

Backed by Andreessen Horowitz and Foundation Capital, and built by leaders from Meta AI, Google ... This is a hands-on, high-ownership IC role for someone who is equally comfortable in Figma and in a ...

Formlabs

Manager, Google Ads

Somerville, MA · On-site

$100K - $160K/yr

Together, we're helping everyone design, prototype, and manufacture faster than ever before. We're ... This is an IC role for someone who's equal parts strategic and operational, and who lets data drive ...

Skip

Product Design Engineer

San Francisco, CA · On-site

$160K - $210K/yr

Skip is a 22-person early-stage start-up that spun out of Google X in 2023. With deep cross ... an IC role. Some of the specific responsibilities include, but are not limited to: * Own core CAD ...

Capital One

Lead Data Engineer-IC

Mclean, VA

$115K - $139K/yr

Collaborate with and across Agile teams to design, develop, test, implement, and support technical ... At least 1 year experience with cloud computing (AWS, Microsoft Azure, Google Cloud) Preferred ...

Capital One

Lead Data Engineer-IC

Mclean, VA · On-site

$115K - $139K/yr

Collaborate with and across Agile teams to design, develop, test, implement, and support technical ... At least 1 year experience with cloud computing (AWS, Microsoft Azure, Google Cloud) Preferred ...

Capital One

Lead Machine Learning Engineer (IC)

Richmond, VA · On-site +1

$101K - $133K/yr

Design, build, and/or deliver ML models and components that solve real-world business problems ... Experience developing and deploying ML solutions in a public cloud such as AWS, Azure, or Google ...

Capital One

Lead Machine Learning Engineer (IC)

Richmond, VA · On-site +1

$101K - $133K/yr

Design, build, and/or deliver ML models and components that solve real-world business problems ... Experience developing and deploying ML solutions in a public cloud such as AWS, Azure, or Google ...

Capital One

Lead Machine Learning Engineer (IC)

New York, NY · On-site

$112K - $147K/yr

Design, build, and/or deliver ML models and components that solve real-world business problems ... Experience developing and deploying ML solutions in a public cloud such as AWS, Azure, or Google ...

Capital One

Lead Machine Learning Engineer (IC)

Mclean, VA · On-site +1

$103K - $136K/yr

Design, build, and/or deliver ML models and components that solve real-world business problems ... Experience developing and deploying ML solutions in a public cloud such as AWS, Azure, or Google ...

Capital One

Lead Machine Learning Engineer (IC)

Manhattan, NY · On-site +1

$112K - $148K/yr

Design, build, and/or deliver ML models and components that solve real-world business problems ... Experience developing and deploying ML solutions in a public cloud such as AWS, Azure, or Google ...

Capital One

Lead Machine Learning Engineer (IC)

Mclean, VA · On-site +1

$103K - $136K/yr

Design, build, and/or deliver ML models and components that solve real-world business problems ... Experience developing and deploying ML solutions in a public cloud such as AWS, Azure, or Google ...

Capital One

Lead Machine Learning Engineer (IC)

San Jose, CA · On-site +1

$120K - $158K/yr

Design, build, and/or deliver ML models and components that solve real-world business problems ... Experience developing and deploying ML solutions in a public cloud such as AWS, Azure, or Google ...

Capital One

Lead Machine Learning Engineer (IC)

Cambridge, MA · On-site +1

$112K - $147K/yr

Design, build, and/or deliver ML models and components that solve real-world business problems ... Experience developing and deploying ML solutions in a public cloud such as AWS, Azure, or Google ...

Capital One

Lead Machine Learning Engineer (IC)

New York, NY · On-site +1

$112K - $147K/yr

Design, build, and/or deliver ML models and components that solve real-world business problems ... Experience developing and deploying ML solutions in a public cloud such as AWS, Azure, or Google ...

LanceSoft Inc

RF Engineer - III

Englewood, CO · On-site

... Design tools like Atoll, MapInfo, Google Earth, Planet Familiar with Samsung / Nokia OEM and ... as an IC with minimal supervision Basic RF Optimization / Performance skills is a plus ...

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Showing results 21-40

All JobsGoogle Ic Design Jobs

Google Ic Design information

See salary details

$80.5K

$139.4K

$182.5K

How much do google ic design jobs pay per year?

As of Aug 11, 2026, the average yearly pay for google ic design in the United States is $139,368.00, according to ZipRecruiter salary data. Most workers in this role earn between $136,000.00 and $136,000.00 per year, depending on experience, location, and employer.

What are some common challenges faced by IC design engineers at Google, and how does the team typically address them?

IC Design Engineers at Google frequently encounter challenges such as managing complex design specifications, meeting tight project timelines, and ensuring seamless integration with other hardware and software teams. To address these, the team emphasizes cross-functional collaboration, regular design reviews, and access to advanced simulation and verification tools. Engineers are encouraged to share knowledge and leverage Google's robust internal resources, which helps in efficiently resolving technical roadblocks and fostering continuous learning.

What is the difference between Google Ic Design vs Google Hardware Design?

AspectGoogle Ic DesignGoogle Hardware Design
Primary FocusIntegrated Circuit (IC) design and developmentHardware product design including devices and components
Required SkillsVLSI, circuit design, verification, CAD toolsElectrical engineering, PCB design, hardware prototyping
Work EnvironmentDesign labs, CAD software, simulation toolsProduct labs, prototyping facilities, manufacturing
Industry UsageSemiconductor, electronics manufacturingConsumer electronics, hardware products

Google Ic Design professionals focus on designing integrated circuits and chips, while Google Hardware Design involves creating complete hardware products. Both roles require electrical engineering skills, but Ic Design is more specialized in circuit development, whereas Hardware Design covers broader product development processes.

What does a Google IC design engineer do?

A Google IC (Integrated Circuit) Design engineer is responsible for designing, developing, and testing microchips and integrated circuits used in Google's hardware products. This includes tasks such as schematic design, layout, verification, and collaborating with cross-functional teams to optimize performance and power consumption. These engineers play a crucial role in ensuring the reliability and efficiency of chips used in devices like smartphones, servers, and other Google hardware. The role often involves using specialized software tools for simulation and validation, as well as staying up-to-date with advancements in semiconductor technology.

What are the key skills and qualifications needed to thrive as a Google IC design engineer?

To thrive as a Google IC Design Engineer, you need a strong background in electrical engineering, digital and analog circuit design, and experience with semiconductor technologies, usually supported by a relevant degree. Proficiency in industry-standard EDA tools (like Cadence, Synopsys, or Mentor Graphics), hardware description languages (such as Verilog or VHDL), and familiarity with silicon verification processes are typically required. Strong problem-solving abilities, collaboration, and effective communication are essential soft skills for success in multidisciplinary teams. These skills and qualifications ensure innovative, reliable chip designs that meet performance benchmarks and integrate seamlessly into complex systems.
More about Google Ic Design jobs
What job categories do people searching Google Ic Design jobs look for? The top searched job categories for Google Ic Design jobs are:
Google Ic Design jobs near you
Infographic showing various Google Ic Design job openings in the United States as of August 2026, with employment types broken down into 10% Internship, and 90% Full Time. Highlights an 70% In-person, 10% Hybrid, and 20% Remote job distribution, with an average salary of $139,368 per year, or $67 per hour.

Senior RTL Designer - Interconnect/NoC Design

TylSemi

San Jose, CA • On-site

Full-time

Posted 27 days ago

Job description

We are looking for SoC Fabric micro-architect and RTL designer for chiplet-based AI and High-Performance Compute silicon development.
What You'll Do
  • Define on-chip fabric topologies connecting the multiple subsystems
  • Specify the data-path fabric for the high-bandwidth routes: bandwidth provisioning, pipeline depth, buffering strategy, and back-pressure propagation between major subsystems.
  • Architect the register-access fabric with address decoding and access-protection logic.
  • Define the arbitration and QoS policy for shared fabric resources: priority assignment per traffic class, bandwidth reservation, and starvation-prevention mechanisms.
  • Own the fabric error-handling architecture: how illegal accesses, timeouts, and protocol violations are detected, logged, and reported to the management subsystem.
  • Own the CDC strategy for every clock-domain boundary on the die - and documenting the timing constraints for each.
  • Own or closely review all fabric RTL: bus bridges, async FIFOs, arbiters, address decoders, and pipeline registers that form the on-chip interconnect.
  • Drive integration assembly: own the top-level connectivity netlist that instantiates all major blocks and wires them through the fabric, serving as the integration point of truth.
  • Coordinate with subsystem leads align on interface protocols, handshake semantics, and reset sequencing at each fabric boundary.
  • Define and own the fabric performance model: estimate bandwidth utilization per path under representative traffic mixes for each operating mode and identify bottlenecks.
  • Establish fabric-level bring-up tests: register accessibility checks, path connectivity tests, and loopback sequences that confirm the interconnect is healthy before full subsystem integration testing begins.
  • Coordinate with the physical design team on fabric floorplan implications: block placement driven by dominant data flow, clock-region boundaries, and wire-length budgets for timing closure.

What We're Looking For
  • BS/MS in Electrical Engineering, Computer Engineering, or equivalent with 8+ years of digital IC design, with at least 4 years owning on-chip interconnect, bus fabric, or NoC architecture at block-lead or integration-lead level.
  • Deep expertise in one or more on-chip interconnect protocols: AXI4 / AXI4-Lite / AXI-Stream; CHI or equivalent; able to write and review bus bridge RTL and understand ordering rules, response channels, and error signaling.
  • Experience with Network-on-Chip (NoC) design or integration of commercial NoC IP (in a complex SoC).
  • Familiarity with AMBA CHI or ACE coherency extensions and their impact on fabric design.
  • Solid understanding of CDC design: async FIFO design, gray-code counters, synchronizer topologies, and CDC verification methodology.
  • Experience owning the top-level integration netlist or chip-level assembly RTL on a multi-block design.
  • Strong SystemVerilog skills: arbiters, FIFOs, pipelines, address decoders, and parameterized bus infrastructure.
  • Experience with static timing constraints for multi-clock designs

Good To Have
  • Background with high-speed chiplet or SoC integration at advanced nodes (7 nm or below), including floorplan-driven bus topology decisions.
  • Experience building or maintaining an automated register-map generation flow (SystemRDL, IP-XACT, or similar).
  • Prior role as chip-level integration lead responsible for assembling subsystem IPs into a complete design.
  • Familiarity with hardware security primitives: access control, firewall IP, or trusted execution region isolation in the fabric.
  • Experience with formal property verification of bus protocols or CDC crossings.

Location
Hybrid/On-site - San Jose, CA / Remote -USA
About TylSemi, Inc.
The Opportunity
The AI infrastructure market is exploding. Every hyperscaler, every cloud provider, every AI company is building custom silicon. But they all face the same problem: how do you connect hundreds of chips, deliver clean power at scale, and move terabits of data without melting the package?
That's what we solve. TylSemi builds the chiplet infrastructure IP - the IO, power delivery, and interconnect building blocks - that makes AI/HPC systems actually work at scale.
This isn't a nice-to-have. It's the critical path.
Why Now
The Market Window
The semiconductor industry is going through its biggest architectural shift in 40 years:
• Moore's Law is dead. 2nm and beyond delivers marginal performance gains. The future is chiplets, not monolithic dies.
• Custom silicon is now mainstream. Google, Microsoft, Amazon, Meta, OpenAI - they're all designing their own ASICs. The $50B custom silicon market is growing 30% annually.
• IO and power are the bottleneck. Solve hard problems and provide something which is a category in itself.
Translation: We're entering the market at exactly the moment when every major AI/HPC player needs what we're building, and their alternatives are disappearing.
Culture & Team: How We Work
No Politics, No Bureaucracy
There are no layers, no approval chains, no corporate theater.
• If you have an idea, we test it. If it works, we ship it.
• No endless meetings, no PowerPoint presentations to convince middle management.
Remote-Friendly, Global Team
• US team: Bay Area preferred, but we hire the best people regardless of location
• India team: Building a world-class design center in Bangalore
Move Fast, Ship Real Products
We're not a research project. We have paying customers, committed capital, and aggressive timelines.
This is a company, not a lifestyle business. We're building to win.
What We Value
• Ownership mindset. You're not here to execute someone else's roadmap. You're here to define it.
• Bias for action. We move fast. Analysis paralysis doesn't fly here.
• Deep technical expertise. This is hard engineering. We need people who've shipped real silicon and debugged real hardware.
• Low ego, high standards. We don't care about titles or politics. We care about results.
The Ask
If you're reading this, you're probably comfortable. You have a good job at a stable company with all the benefits.
We're asking you to walk away from that and bet on us.
Here's why you should:
• The market is real. AI infrastructure spending is $200B+ annually and growing 40% YoY. Every hyperscaler needs what we're building.
• The team has done this before. We've built and exited semiconductor companies at scale. This isn't our first rodeo.
• The traction is de-risked. We have LOIs, strategic investors, and a clear path to revenue.
• The work is consequential. You're not optimizing someone's ad click-through rate. You're building the silicon infrastructure that powers AI.
This is the bet. Join us and build something that matters.
Or stay comfortable. No judgment.
But if you're the kind of person who wants to take the shot, we'd love to talk.
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