ZipRecruiter

Log In

1

Google Fpga Jobs (NOW HIRING)

Google Inc.

RTL Design Engineer, Silicon

Mountain View, CA · On-site

$138 - $197/hr

... FPGA and emulation platforms. * Knowledge of ASIC Verification or DFT. About the job Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google ...

JS Consulting

Senior Verification Engineer

New York, NY · On-site

$114K - $157K/yr

From Google: An FPGA, or Field-Programmable Gate Array, is an integrated circuit that can be configured and reconfigured after manufacturing to perform a specific hardware task. Unlike a fixed ...

SECURE RPO LLC

Software Engineer

Lexington, MA · On-site

OpenMP, Threads, Real-Time Priorities, CUDA, FPGA * Python/TensorFlow * Web Application Development Software * Cloud-Based Solutions (e.g. AWS, Azure, Google) Background/Need The Secure Resilient ...

Prattwhitney

$132.40 - $251.60/hr

Proficiency in building and maintaining a code base using CMake and Google Test. * Valid U.S ... Knowledge of FPGA, bare‑metal firmware, and Linux Kernel driver development. * Experience with ...

Aalyria

Communications DSP Engineer

$185K - $215K/yr

With technology acquired from Google, Aalyria is at the forefront of innovation in satellite and ... You'll collaborate closely with cross-functional teams spanning ASIC/FPGA design, RF/optical ...

Architect Labs

$210 - $360/hr

... Anthropic, Google DeepMind, Meta SuperIntelligence, xAI, Apple and Intel. What You'll Do As a ... Support FPGA prototyping on Xilinx for early functional validation of the fabric, including multi ...

previous pagenext page

Showing results 21-40

All JobsTechnology JobsGoogle Fpga Jobs

Google Fpga information

See salary details

$85K

$147.3K

$198.5K

How much do google fpga jobs pay per year?

As of Sep 7, 2026, the average yearly pay for google fpga in the United States is $147,315.00, according to ZipRecruiter salary data. Most workers in this role earn between $130,000.00 and $167,000.00 per year, depending on experience, location, and employer.

What is a Google FPGA?

A Google FPGA job typically involves designing, optimizing, and implementing FPGA-based hardware accelerators to improve computing performance for Google's infrastructure. Engineers in this role work on hardware-software co-design, RTL development, and performance tuning for applications like machine learning, networking, and data processing. They collaborate with software and hardware teams to integrate FPGA solutions into Google's data centers and cloud services. Strong skills in FPGA development, Verilog/SystemVerilog, and hardware design are essential.

What types of projects do Google FPGA engineers typically work on, and how do they collaborate with other teams?

Google FPGA engineers are involved in designing, prototyping, and optimizing custom hardware accelerators and infrastructure solutions that support large-scale data processing, networking, and machine learning applications. They frequently work on cross-functional projects, collaborating closely with software engineers, system architects, and product teams to translate high-level requirements into efficient hardware solutions. Daily responsibilities might include developing RTL code, running simulations, debugging hardware, and participating in design reviews. This role offers significant opportunities for professional growth by working on innovative technologies, and exposure to a wide variety of technical challenges alongside some of the industry's leading experts.

What are the key skills and qualifications needed to thrive in the Google FPGA position, and why are they important?

To excel as a Google FPGA engineer, you need a strong background in digital hardware design, FPGA development, and proficiency in hardware description languages like Verilog or VHDL, typically supported by a degree in electrical or computer engineering. Familiarity with FPGA toolchains (such as Xilinx Vivado or Intel Quartus), simulation tools, and relevant industry certifications are highly valued. Strong problem-solving skills, teamwork, and effective communication are essential for success in collaborative, fast-paced environments. These abilities ensure that complex hardware solutions are effectively designed, debugged, and integrated with Google's advanced technology infrastructure.

More about Google Fpga jobs

What cities are hiring for Google Fpga jobs?

Cities with the most Google Fpga job openings:

What are the most commonly searched types of Google Fpga jobs?

The most popular types of Google Fpga jobs are:

What states have the most Google Fpga jobs?

States with the most job openings for Google Fpga jobs include:

What job categories do people searching Google Fpga jobs look for?

The top searched job categories for Google Fpga jobs are:

Google Fpga jobs near you
Infographic showing various Google Fpga job openings in the United States as of August 2026, with employment types broken down into 88% Full Time, 8% Part Time, and 4% Contract. Highlights an 70% Physical, 3% Hybrid, and 27% Remote job distribution, with an average salary of $147,315 per year, or $70.8 per hour.

RTL Design Engineer, Silicon

Google Inc.

Mountain View, CA • On-site

$138 - $197/hr

Other

Posted 23 days ago

Google rating

8.8

Company rating: 8.8 out of 10

Based on 103 frontline employees who took The Breakroom Quiz

48th of 247 rated software companies

Job description

Google Mountain View, CA, USA

Mid

Experience driving progress, solving problems, and mentoring more junior team members; deeper expertise and applied knowledge within relevant area.

Share RTL Design Engineer, Silicon

  • Copy link

X In most instances, this position requires in-person interviews as part of the hiring process.

  • Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.
  • 4 years of experience with IP development or integration.
  • Experience in ASIC development withVerilogor VHDL.
  • Experience with a scripting language like Perl or Python.
Preferred qualifications:
  • Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
  • Experience with ASIC design methodologies for clock domain checks, reset checks and low power design.
  • Knowledge of one of these areas: processor cores, buses/fabric/NoC, debug/trace, interrupts, clocks/reset.
  • Knowledge of high-performance and energy efficient design techniques.
  • Knowledge of FPGA and emulation platforms.
  • Knowledge of ASIC Verification or DFT.
About the job

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.

Individual pay is determined by factors including job-related skills, experience, and relevant education or training.

About the job

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.

Individual pay is determined by factors including job-related skills, experience, and relevant education or training.

US: $138000 - $197000 (USD) + 15% bonus target + equity + benefits
Learn more about benefits at Google .

  • Define microarchitecture for a subsystem.
  • Integrate internal and/or external IP.
  • Define microarchitecture of a small to medium size IP.
  • Perform RTL coding, function/performance simulation debug and Lint/CDC/FV/UPF checks.
  • Participate in test plan and coverage analysis of the sub-system and chip-level verification.

Google is proud to be an equal opportunity and affirmative action employer. We are committed to building a workforce that is representative of the users we serve, creating a culture of belonging, and providing an equal employment opportunity regardless of race, creed, color, religion, gender, sexual orientation, gender identity/expression, national origin, disability, age, genetic information, veteran status, marital status, pregnancy or related condition (including breastfeeding), expecting or parents-to-be, criminal histories consistent with legal requirements, or any other basis protected by law. See also Google's EEO Policy , Know your rights: workplace discrimination is illegal , Belonging at Google , and How we hire .

Google is a global company and, in order to facilitate efficient collaboration and communication globally, English proficiency is a requirement for all roles unless stated otherwise in the job posting.

To all recruitment agencies: Google does not accept agency resumes. Please do not forward resumes to our jobs alias, Google employees, or any other organization location. Google is not responsible for any fees related to unsolicited resumes.

Equity is granted exclusively and discretionarily by Alphabet Inc. on the basis of an agreement concluded between you and Alphabet Inc. Alphabet Inc. is your sole contractual partner with respect to equity grants. GSU grants are not guaranteed, are discretionary, are subject to approval by the Alphabet Inc. board of directors or its delegate, the terms of the relevant Alphabet Inc. stock plan, and your grant agreement. They have no impact on statutory payments. Current or past grants do not confer an acquired right.

#J-18808-Ljbffr

What Google employees say

Pay

Benefits

Hours and flexibility

Workplace

Get the full story on Breakroom

Apply