Experience with ASIC design methodologies for clock domain checks, reset checks and low power ... Google's mission is to organize the world's information and make it universally accessible and ...
Experience with ASIC design methodologies for clock domain checks, reset checks and low power ... Google's mission is to organize the world's information and make it universally accessible and ...
Experience in ASIC development with Verilog or VHDL (Vhsic Hardware Description Language ... Google's mission is to organize the world's information and make it universally accessible and ...
Experience in ASIC development with Verilog or VHDL (Vhsic Hardware Description Language ... Google's mission is to organize the world's information and make it universally accessible and ...
Senior ASIC Design Verification Engineer, Google Cloud (Sunnyvale)
Sunnyvale, CA · On-site
$156K - $229K/yr
Learn more about benefits at Google . Responsibilities * Plan the verification of complex digital design blocks by understanding the design specification and interacting with design engineers to ...
Senior ASIC Design Verification Engineer, Google Cloud (Sunnyvale)
Sunnyvale, CA · On-site
$156K - $229K/yr
Learn more about benefits at Google . Responsibilities * Plan the verification of complex digital design blocks by understanding the design specification and interacting with design engineers to ...
RTL Design Engineer, TPU
Sunnyvale, CA · On-site
$200 - $250/hr
Google, Sunnyvale, CA, USA Qualifications * Bachelor's degree in Electrical Engineering, Computer ... Develop SystemVerilog RTL to implement logic for ASIC products according to coding and quality ...
RTL Design Engineer, TPU
Sunnyvale, CA · On-site
$200 - $250/hr
Google, Sunnyvale, CA, USA Qualifications * Bachelor's degree in Electrical Engineering, Computer ... Develop SystemVerilog RTL to implement logic for ASIC products according to coding and quality ...
Principal Analog/Mixed-Signal ASIC Engineer
Sunnyvale, CA · On-site
$237K/yr
About the Team Born at X, Google's Moonshot Factory, Taara is on a mission to connect billions of ... Contribute to ASIC design and layout, system-level optimization, and product strategy.
Principal Analog/Mixed-Signal ASIC Engineer
Sunnyvale, CA · On-site
$237K/yr
About the Team Born at X, Google's Moonshot Factory, Taara is on a mission to connect billions of ... Contribute to ASIC design and layout, system-level optimization, and product strategy.
... of experience in ASIC design or RTL design. * Experience with SoC design and integration ... We empower Google customers with breakthrough capabilities and insights by delivering AI and ...
... of experience in ASIC design or RTL design. * Experience with SoC design and integration ... We empower Google customers with breakthrough capabilities and insights by delivering AI and ...
RTL Design Engineer, TPU
Sunnyvale, CA · On-site
... Google . Responsibilities * Work separately to create and review management and control subsystem's design microarchitecture specifications. * Develop SystemVerilog RTL to implement logic for ASIC ...
RTL Design Engineer, TPU
Sunnyvale, CA · On-site
... Google . Responsibilities * Work separately to create and review management and control subsystem's design microarchitecture specifications. * Develop SystemVerilog RTL to implement logic for ASIC ...
RTL Design Engineer, Silicon
Mountain View, CA · On-site
$150 - $200/hr
Google Mountain View, CA, USA Mid Experience driving progress, solving problems, and mentoring more ... Experience with ASIC design methodologies for clock domain checks, reset checks and low power ...
RTL Design Engineer, Silicon
Mountain View, CA · On-site
$150 - $200/hr
Google Mountain View, CA, USA Mid Experience driving progress, solving problems, and mentoring more ... Experience with ASIC design methodologies for clock domain checks, reset checks and low power ...
... Google . Responsibilities * Work separately to create and review management and control subsystem's design microarchitecture specifications. * Develop SystemVerilog RTL to implement logic for ASIC ...
... Google . Responsibilities * Work separately to create and review management and control subsystem's design microarchitecture specifications. * Develop SystemVerilog RTL to implement logic for ASIC ...
This is a cross-functional and central role that will require interactions with numerous ASIC ... design tools, flows, and methodologies. Information collected and processed as part of your Google ...
This is a cross-functional and central role that will require interactions with numerous ASIC ... design tools, flows, and methodologies. Information collected and processed as part of your Google ...
TPU SoC Integration Engineer, Cloud
Sunnyvale, CA · On-site
$150 - $200/hr
... of experience in ASIC design or RTL design. * Experience with SoC design and integration ... We empower Google customers with breakthrough capabilities and insights by delivering AI and ...
TPU SoC Integration Engineer, Cloud
Sunnyvale, CA · On-site
$150 - $200/hr
... of experience in ASIC design or RTL design. * Experience with SoC design and integration ... We empower Google customers with breakthrough capabilities and insights by delivering AI and ...
Silicon Physical Design Engineer
Sunnyvale, CA · On-site
$125 - $150/hr
Google - Physical Design Engineer, Sunnyvale, CA, USA Required qualifications * Bachelor's degree ... Experience in block/subchip level place and route for SoC or with multiple-cycles of SoC in ASIC ...
Silicon Physical Design Engineer
Sunnyvale, CA · On-site
$125 - $150/hr
Google - Physical Design Engineer, Sunnyvale, CA, USA Required qualifications * Bachelor's degree ... Experience in block/subchip level place and route for SoC or with multiple-cycles of SoC in ASIC ...
Senior ASIC Physical Design Engineer
Sunnyvale, CA · On-site
$150 - $200/hr
# Senior ASIC Physical Design EngineerGoogle • onsite • 111 W Java Dr, Sunnyvale, CA 94089, USA ... USD 156000.00 - USD 229000.00 / unspecifiedBusinesses of all shapes and sizes rely on Google ...
Senior ASIC Physical Design Engineer
Sunnyvale, CA · On-site
$150 - $200/hr
# Senior ASIC Physical Design EngineerGoogle • onsite • 111 W Java Dr, Sunnyvale, CA 94089, USA ... USD 156000.00 - USD 229000.00 / unspecifiedBusinesses of all shapes and sizes rely on Google ...
ASIC Design Verification Engineer
Mountain View, CA · On-site
$175K - $215K/yr
Since its start as the Google Self-Driving Car Project in 2009, Waymo has focused on building the ... Partner with design and architecture teams to translate hardware specifications into comprehensive ...
ASIC Design Verification Engineer
Mountain View, CA · On-site
$175K - $215K/yr
Since its start as the Google Self-Driving Car Project in 2009, Waymo has focused on building the ... Partner with design and architecture teams to translate hardware specifications into comprehensive ...
ASIC Formal Verification Engineer, Google Cloud
Sunnyvale, CA · On-site
$132 - $189/hr
... design verification. * Experience with SystemVerilog or Verilog. * Experience working with one or ... As an ASIC Formal Verification Engineer, you will contribute formal verification expertise to ...
ASIC Formal Verification Engineer, Google Cloud
Sunnyvale, CA · On-site
$132 - $189/hr
... design verification. * Experience with SystemVerilog or Verilog. * Experience working with one or ... As an ASIC Formal Verification Engineer, you will contribute formal verification expertise to ...
... ASIC engineers. As a Soc Design Engineer on the TPU team, you will be a key contributor to the development of Google's AI accelerators. You will leverage your expertise in digital logic design ...
... ASIC engineers. As a Soc Design Engineer on the TPU team, you will be a key contributor to the development of Google's AI accelerators. You will leverage your expertise in digital logic design ...
... or ASIC/SoC design. * Experience with SystemVerilog Assertions (SVA) and formal verification ... We empower Google customers with breakthrough capabilities and insights by delivering AI and ...
... or ASIC/SoC design. * Experience with SystemVerilog Assertions (SVA) and formal verification ... We empower Google customers with breakthrough capabilities and insights by delivering AI and ...
Physical Low Power Validation Engineer
Sunnyvale, CA · On-site
$159K - $164K/yr
... ASIC design environment. * Experience in static low-power rule checking tools (e.g., VCLP or CLP ... We empower Google customers with breakthrough capabilities and insights by delivering AI and ...
Physical Low Power Validation Engineer
Sunnyvale, CA · On-site
$159K - $164K/yr
... ASIC design environment. * Experience in static low-power rule checking tools (e.g., VCLP or CLP ... We empower Google customers with breakthrough capabilities and insights by delivering AI and ...
TPU SoC Design Engineer, Cloud
Sunnyvale, CA · On-site
$150 - $200/hr
... ASIC engineers. As a Soc Design Engineer on the TPU team, you will be a key contributor to the development of Google's AI accelerators. You will leverage your expertise in digital logic design ...
TPU SoC Design Engineer, Cloud
Sunnyvale, CA · On-site
$150 - $200/hr
... ASIC engineers. As a Soc Design Engineer on the TPU team, you will be a key contributor to the development of Google's AI accelerators. You will leverage your expertise in digital logic design ...
Silicon Hardware Emulation Engineer, Google Cloud
Sunnyvale, CA · On-site
$144K - $191K/yr
... design, and assisting in the hardware and lab bring up and verification of our ASIC systems. The AI and Infrastructure team is redefining what's possible. We empower Google customers with ...
Silicon Hardware Emulation Engineer, Google Cloud
Sunnyvale, CA · On-site
$144K - $191K/yr
... design, and assisting in the hardware and lab bring up and verification of our ASIC systems. The AI and Infrastructure team is redefining what's possible. We empower Google customers with ...
Google Asic Design information
See California salary details
$92.8K - $102.5K
16% of jobs
$102.5K - $112.1K
3% of jobs
$112.1K - $121.8K
4% of jobs
$124.7K is the 25th percentile. Wages below this are outliers.
$121.8K - $131.5K
6% of jobs
The median wage is $137.6K / yr.
$131.5K - $141.2K
33% of jobs
$141.2K - $150.9K
3% of jobs
$150.9K - $160.6K
2% of jobs
$167K is the 75th percentile. Wages above this are outliers.
$160.6K - $170.3K
12% of jobs
$170.3K - $180K
5% of jobs
$180K - $189.7K
4% of jobs
$189.7K - $199.4K
12% of jobs
$92.8K
$148.2K
$199.4K
How much do google asic design jobs pay per year?
As of Sep 8, 2026, the average yearly pay for google asic design in California is $148,229.00, according to ZipRecruiter salary data. Most workers in this role earn between $129,800.00 and $177,600.00 per year, depending on experience, location, and employer.
What is a Google ASIC Design?
A Google ASIC Design job involves developing custom application-specific integrated circuits (ASICs) to optimize performance, power efficiency, and functionality for Google's hardware infrastructure. Engineers in this role work on architecture, design, verification, and testing of ASICs used in data centers, AI accelerators, and other specialized hardware. They collaborate with cross-functional teams to refine system requirements and ensure successful silicon implementation. Strong expertise in digital design, hardware description languages (HDLs) like Verilog or VHDL, and synthesis tools is essential.
What does a Google ASIC Design engineer do?
As a Google ASIC Design engineer, your daily responsibilities typically involve defining microarchitectures, designing and verifying digital circuits, running design simulations, and collaborating closely with verification, software, and hardware teams. You’ll use advanced EDA tools to implement and optimize circuits, ensuring they meet strict specifications for power, performance, and area. Regular design reviews, cross-functional brainstorming sessions, and debugging activities are part of the routine. This collaborative environment fosters continual learning and innovation, providing opportunities for both technical growth and career advancement.
What are the key skills and qualifications needed to thrive in the Google ASIC Design position?
To thrive as a Google ASIC Design engineer, you need a solid background in electrical engineering, digital logic design, and experience with ASIC design methodologies. Proficiency with industry-standard EDA tools such as Synopsys, Cadence, or Mentor Graphics, along with scripting languages like Python or TCL, is essential, and a relevant certification or advanced degree can be advantageous. Strong analytical thinking, teamwork, and clear communication skills are highly valued in this role. These skills ensure high-quality, efficient chip designs that meet rigorous performance, power, and area requirements within a collaborative and fast-paced environment.
What are popular job titles related to Google Asic Design jobs in California?
For Google Asic Design jobs in California, the most frequently searched job titles are:
What job categories do people searching Google Asic Design jobs in California look for?
The top searched job categories for Google Asic Design jobs in California are:
What cities in California are hiring for Google Asic Design jobs?
Cities in California with the most Google Asic Design job openings:
Google rating
8.8
Based on 103 frontline employees who took The Breakroom Quiz
48th of 247 rated software companies
Job description
info_outline
X In most instances, this position requires in-person interviews as part of the hiring process.
Minimum qualifications:
Preferred qualifications:
About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.
Individual pay is determined by factors including job-related skills, experience, and relevant education or training.
US: $138000 - $197000 (USD) 15% bonus target equity benefits
Learn more about benefits at Google .
Responsibilities
Information collected and processed as part of your Google Careers profile, and any job applications you choose to submit is subject to Google's Applicant and Candidate Privacy Policy .
Google is proud to be an equal opportunity and affirmative action employer. We are committed to building a workforce that is representative of the users we serve, creating a culture of belonging, and providing an equal employment opportunity regardless of race, creed, color, religion, gender, sexual orientation, gender identity/expression, national origin, disability, age, genetic information, veteran status, marital status, pregnancy or related condition (including breastfeeding), expecting or parents-to-be, criminal histories consistent with legal requirements, or any other basis protected by law. See also Google's EEO Policy , Know your rights: workplace discrimination is illegal , Belonging at Google , and How we hire .
If you have a need that requires accommodation, please let us know by completing our Accommodations for Applicants form .
Google is a global company and, in order to facilitate efficient collaboration and communication globally, English proficiency is a requirement for all roles unless stated otherwise in the job posting.
To all recruitment agencies: Google does not accept agency resumes. Please do not forward resumes to our jobs alias, Google employees, or any other organization location. Google is not responsible for any fees related to unsolicited resumes.
Equity is granted exclusively and discretionarily by Alphabet Inc. on the basis of an agreement concluded between you and Alphabet Inc. Alphabet Inc. is your sole contractual partner with respect to equity grants. GSU grants are not guaranteed, are discretionary, are subject to approval by the Alphabet Inc. board of directors or its delegate, the terms of the relevant Alphabet Inc. stock plan, and your grant agreement. They have no impact on statutory payments. Current or past grants do not confer an acquired right.
X In most instances, this position requires in-person interviews as part of the hiring process.
Minimum qualifications:
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.
- 4 years of experience with IP development or integration.
- Experience in ASIC development withVerilogor VHDL.
- Experience with a scripting language like Perl or Python.
Preferred qualifications:
- Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
- Experience with ASIC design methodologies for clock domain checks, reset checks and low power design.
- Knowledge of one of these areas: processor cores, buses/fabric/NoC, debug/trace, interrupts, clocks/reset.
- Knowledge of high-performance and energy efficient design techniques.
- Knowledge of FPGA and emulation platforms.
- Knowledge of ASIC Verification or DFT.
About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.
Individual pay is determined by factors including job-related skills, experience, and relevant education or training.
US: $138000 - $197000 (USD) 15% bonus target equity benefits
Learn more about benefits at Google .
Responsibilities
- Define microarchitecture for a subsystem.
- Integrate internal and/or external IP.
- Define microarchitecture of a small to medium size IP.
- Perform RTL coding, function/performance simulation debug and Lint/CDC/FV/UPF checks.
- Participate in test plan and coverage analysis of the sub-system and chip-level verification.
Information collected and processed as part of your Google Careers profile, and any job applications you choose to submit is subject to Google's Applicant and Candidate Privacy Policy .
Google is proud to be an equal opportunity and affirmative action employer. We are committed to building a workforce that is representative of the users we serve, creating a culture of belonging, and providing an equal employment opportunity regardless of race, creed, color, religion, gender, sexual orientation, gender identity/expression, national origin, disability, age, genetic information, veteran status, marital status, pregnancy or related condition (including breastfeeding), expecting or parents-to-be, criminal histories consistent with legal requirements, or any other basis protected by law. See also Google's EEO Policy , Know your rights: workplace discrimination is illegal , Belonging at Google , and How we hire .
If you have a need that requires accommodation, please let us know by completing our Accommodations for Applicants form .
Google is a global company and, in order to facilitate efficient collaboration and communication globally, English proficiency is a requirement for all roles unless stated otherwise in the job posting.
To all recruitment agencies: Google does not accept agency resumes. Please do not forward resumes to our jobs alias, Google employees, or any other organization location. Google is not responsible for any fees related to unsolicited resumes.
Equity is granted exclusively and discretionarily by Alphabet Inc. on the basis of an agreement concluded between you and Alphabet Inc. Alphabet Inc. is your sole contractual partner with respect to equity grants. GSU grants are not guaranteed, are discretionary, are subject to approval by the Alphabet Inc. board of directors or its delegate, the terms of the relevant Alphabet Inc. stock plan, and your grant agreement. They have no impact on statutory payments. Current or past grants do not confer an acquired right.
About Google
Sourced by ZipRecruiter
Industry
Software development and technology, communication and media
Company size
10,000+ Employees
Headquarters location
Mountain View, CA, US