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Google Asic Design Engineer Jobs in Raleigh, NC (NOW HIRING)

Marvell

Senior Staff Engineer, Physical Design

Morrisville, NC · On-site

$127K - $131K/yr

Your Team, Your Impact Built on decades of expertise and execution, Marvell's custom Processor/ASIC ... design process. This position also provides an exciting platform to engage with diverse engineering ...

Avnet, Inc.

Field Application Engineer

Raleigh, NC

Develop relationships with and become trusted advisor to (system) engineers & architects in your ... Experience with and understanding at systems level, FPGA and ASIC design tools. Experience with ...

Telus Digital

Google CX Engineer

Durham, NC · On-site +1

Design and implement secure integrations between GECX, Google Cloud AI services and external ... Bachelor's degree in Computer Science, Engineering, Business, or related field; advanced degree is ...

Telus Digital

Google Cloud Engineer (GECX)

Durham, NC · On-site +1

$53.75 - $72/hr

Design and implement secure integrations between GECX, Google Cloud AI services and external ... Bachelor's degree in Computer Science, Engineering, Business, or related field; advanced degree is ...

Nvidia

Senior ASIC Timing Engineer

Durham, NC · Hybrid

We are now looking for a motivated ASIC Timing Engineer to join our dynamic and growing team. If ... Experience in physical design and optimization e.g., synthesis, placement, routing, logic ...

Google

Senior Software Engineer

Raleigh, NC · On-site

$119K - $157K/yr

... UI design and mobile; the list goes on and is growing every day. As a software engineer, you will work on a specific project critical to Google's needs with opportunities to switch teams and ...

Google

Software Engineer III

Raleigh, NC · On-site

$56 - $75/hr

About the job Google's software engineers develop the next-generation technologies that change how ... You will design, develop, test, deploy, maintain, and enhance software solutions. Individual pay is ...

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All JobsGoogle Asic Design Engineer JobsGoogle Asic Design Engineer Jobs in Raleigh, NC

Google Asic Design Engineer information

See Raleigh, NC salary details

$91.4K

$146K

$196.3K

How much do google asic design engineer jobs pay per year?

As of Jun 16, 2026, the average yearly pay for google asic design engineer in Raleigh, NC is $145,994.00, according to ZipRecruiter salary data. Most workers in this role earn between $127,800.00 and $175,000.00 per year, depending on experience, location, and employer.

What is the difference between Google Asic Design Engineer vs Google FPGA Design Engineer?

AspectGoogle Asic Design EngineerGoogle FPGA Design Engineer
Required CredentialsBachelor's/Master's in Electrical Engineering or Computer Engineering; experience in ASIC designBachelor's/Master's in Electrical Engineering or Computer Engineering; FPGA design experience
Work EnvironmentDesigning custom silicon chips for Google productsDeveloping and testing FPGA prototypes for hardware acceleration
Employer & Industry UsagePrimarily in semiconductor and hardware design teams at GoogleHardware prototyping and acceleration teams at Google

The main difference between a Google Asic Design Engineer and a Google FPGA Design Engineer lies in their focus: ASIC engineers design custom chips for optimized performance, while FPGA engineers develop flexible hardware prototypes using field-programmable gate arrays. Both roles require strong electrical engineering skills but serve different stages of hardware development.

How does a Google ASIC Design Engineer typically collaborate with cross-functional teams during the chip development process?

As a Google ASIC Design Engineer, you will work closely with teams such as architecture, verification, software, and hardware validation to ensure successful chip delivery. Collaboration often involves regular meetings to align on design specifications, resolve integration issues, and discuss performance optimization. Effective communication is essential, as you’ll need to translate requirements from system architects into detailed hardware designs and provide feedback to verification and validation teams. This cross-functional interaction fosters a dynamic work environment and helps ensure the final product meets Google's rigorous standards.

What does a Google ASIC Design Engineer do?

A Google ASIC Design Engineer is responsible for designing and developing custom integrated circuits, known as Application-Specific Integrated Circuits (ASICs), that power Google's data centers, cloud infrastructure, and consumer devices. Their work involves collaborating with cross-functional teams to define requirements, create architecture, perform logic and physical design, and validate the silicon before production. They use advanced design tools and methodologies to ensure high performance, low power consumption, and reliability. Ultimately, their contributions help improve the efficiency and capabilities of Google's hardware products.

What are the key skills and qualifications needed to thrive as a Google ASIC Design Engineer, and why are they important?

To thrive as a Google ASIC Design Engineer, you need a strong background in electrical engineering, digital logic design, and experience with ASIC development, typically backed by a relevant degree. Familiarity with hardware description languages (such as Verilog or VHDL), EDA tools (like Synopsys or Cadence), and an understanding of SoC architectures are essential, and related certifications can be valuable. Strong problem-solving skills, attention to detail, and effective teamwork and communication abilities help set candidates apart. These skills are crucial for designing reliable, high-performance ASICs that meet Google's specifications and project timelines.
What are popular job titles related to Google Asic Design Engineer jobs in Raleigh, NC? For Google Asic Design Engineer jobs in Raleigh, NC, the most frequently searched job titles are:
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Google Asic Design Engineer jobs near you
Senior Principal Engineer, Design Verification

Senior Principal Engineer, Design Verification

Marvell Technology, Inc.

Morrisville, NC • On-site

Full-time

Life, Retirement

Posted 7 days ago

Job description

About Marvell
Marvell's semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities.
At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.
Your Team, Your Impact
Marvell's CXL Product Development team works on groundbreaking innovations for the composable datacenter. We are looking for individuals with a deep understanding and passion for ASIC verification to craft creative solutions for DV architecture, verification and post-silicon validation on some of the industry's most complex semiconductor chips. If you're creative and autonomous, we want to hear from you! At Marvell, you will have the opportunity to shape some of the most incredible products to address the needs of the next generation datacenters.
What You Can Expect
As a member of a dynamic ASIC development team, the candidate will be responsible for leading verification architecture, execution, delivery, post silicon validation , emulation of the next generation ASICs under development working closely with cross functional teams. The member will also have an opportunity to leverage the experience to drive the ASIC front end ASIC development process, emulation, PSV, tools and methodologies leading to the successful ASIC products.
What We're Looking For
  • Bachelor's degree in Computer Science, Electrical Engineering or related fields and 20+ years of related professional experience.
  • Master's degree in Computer Science, Electrical Engineering or related fields with 18+ years of experience.PhD in Computer Science, Electrical Engineering or related fields with 12+ years of experience.
  • Strong understanding of ASIC development process, tools and verification methodologies.
  • Demonstrated track record of leading verification and delivery high quality ASICs.
  • Hands-on experience in verification of multiple SoC architectures, processor cores, memory subsystems and peripheral interfaces.
  • Hands-on experience of bringing up multiple ASICs in the lab.
  • Hands-on experience in driving emulation efforts leading to successful tapeout
  • Proven ability of leading ASIC development teams.
  • Excellent communication, interpersonal and presentation skills.
  • Strong cross-functional leadership skills.
  • Highly motivated, self-driven and ability to drive adoption of new methodologies.

Expected Base Pay Range (USD)
184,400 - 272,950, $ per annum
The successful candidate's starting base pay will be determined based on job-related skills, experience, qualifications, work location and market conditions. The expected base pay range for this role may be modified based on market conditions.
Additional Compensation and Benefit Elements
Marvell is committed to providing exceptional, comprehensive benefits that support our employees at every stage - from internship to retirement and through life's most important moments. Our offerings are built around four key pillars: financial well-being, family support, mental and physical health, and recognition. Highlights include an employee stock purchase plan with a 2-year look back, family support programs to help balance work and home life, robust mental health resources to prioritize emotional well-being, and a recognition and service awards to celebrate contributions and milestones. We look forward to sharing more with you during the interview process.
All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.
Any applicant who requires a reasonable accommodation during the selection process should contact Marvell HR Helpdesk at TAOps@marvell.com.
Interview Integrity
To support fair and authentic hiring practices, candidates are not permitted to use AI tools (such as transcription apps, real-time answer generators like ChatGPT or Copilot, or automated note-taking bots) during interviews.
These tools must not be used to record, assist with, or enhance responses in any way. Our interviews are designed to evaluate your individual experience, thought process, and communication skills in real time. Use of AI tools without prior instruction from the interviewer will result in disqualification from the hiring process.
This position may require access to technology and/or software subject to U.S. export control laws and regulations, including the Export Administration Regulations (EAR). As such, applicants must be eligible to access export-controlled information as defined under applicable law. Marvell may be required to obtain export licensing approval from the U.S. Department of Commerce and/or the U.S. Department of State. Except for U.S. citizens, lawful permanent residents, or protected individuals as defined by 8 U.S.C. 1324b(a)(3), all applicants may be subject to an export license review process prior to employment.
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