Westford, MA · On-site
$141.40K - $145.50K/yr
NVIDIA is looking for best-in-class Senior Physical Design Engineers to join our outstanding Networking Silicon engineering team, developing the industry's best high speed communication devices ...
Westford, MA · On-site
$141.40K - $145.50K/yr
NVIDIA is looking for best-in-class Senior Physical Design Engineers to join our outstanding Networking Silicon engineering team, developing the industry's best high speed communication devices ...
Westford, MA · On-site
$141.40K - $145.50K/yr
NVIDIA is looking for best-in-class Senior Physical Design Engineers to join our outstanding Networking Silicon engineering team, developing the industry's best high speed communication devices ...
Westford, MA · On-site
$141.40K - $145.50K/yr
NVIDIA is looking for best-in-class Senior Physical Design Engineers to join our outstanding Networking Silicon engineering team, developing the industry's best high speed communication devices ...
Beaverton, OR · On-site
$141.50K - $145.70K/yr
As a CPU Physical Design Engineer, you will drive or participate in the following: • Drive RTL-to-GDS design convergence through logic synthesis and place-and-route tools targeting ambitious PPA ...
Beaverton, OR · On-site
$141.50K - $145.70K/yr
As a CPU Physical Design Engineer, you will drive or participate in the following: • Drive RTL-to-GDS design convergence through logic synthesis and place-and-route tools targeting ambitious PPA ...
San Jose, CA · On-site
$141.30K - $226K/yr
Broadcom is searching for an ASIC top level floorplan Physical Design Engineer to join the Asic Products Division. This position involves working with the latest technology to continue driving next ...
San Jose, CA · On-site
$141.30K - $226K/yr
Broadcom is searching for an ASIC top level floorplan Physical Design Engineer to join the Asic Products Division. This position involves working with the latest technology to continue driving next ...
San Jose, CA · On-site
$120K - $192K/yr
Broadcom is searching for an ASIC top level floorplan Physical Design Engineer to join the Asic Products Division. This position involves working with the latest technology to continue driving next ...
San Jose, CA · On-site
$120K - $192K/yr
Broadcom is searching for an ASIC top level floorplan Physical Design Engineer to join the Asic Products Division. This position involves working with the latest technology to continue driving next ...
Sunnyvale, CA · Hybrid
$159.60K - $164.30K/yr
Principal Physical Design Engineer This role has been designed as 'Hybrid' with an expectation that you will work on average 2 days per week from an HPE office. Who We Are: Hewlett Packard Enterprise ...
Sunnyvale, CA · Hybrid
$159.60K - $164.30K/yr
Principal Physical Design Engineer This role has been designed as 'Hybrid' with an expectation that you will work on average 2 days per week from an HPE office. Who We Are: Hewlett Packard Enterprise ...
Sunnyvale, CA · Hybrid
$159.60K - $164.30K/yr
Principal Physical Design Engineer This role has been designed as 'Hybrid' with an expectation that you will work on average 2 days per week from an HPE office. Who We Are: Hewlett Packard Enterprise ...
Sunnyvale, CA · Hybrid
$159.60K - $164.30K/yr
Principal Physical Design Engineer This role has been designed as 'Hybrid' with an expectation that you will work on average 2 days per week from an HPE office. Who We Are: Hewlett Packard Enterprise ...
Sunnyvale, CA · Hybrid
$159.60K - $164.30K/yr
Principal Physical Design Engineer This role has been designed as 'Hybrid' with an expectation that you will work on average 2 days per week from an HPE office. Who We Are: Hewlett Packard Enterprise ...
Sunnyvale, CA · Hybrid
$159.60K - $164.30K/yr
Principal Physical Design Engineer This role has been designed as 'Hybrid' with an expectation that you will work on average 2 days per week from an HPE office. Who We Are: Hewlett Packard Enterprise ...
Beaverton, OR · On-site
$141.50K - $145.70K/yr
As a CPU Physical Design Engineer, you will drive or participate in the following: • Drive RTL-to-GDS design convergence through logic synthesis and place-and-route tools targeting ambitious PPA ...
Beaverton, OR · On-site
$141.50K - $145.70K/yr
As a CPU Physical Design Engineer, you will drive or participate in the following: • Drive RTL-to-GDS design convergence through logic synthesis and place-and-route tools targeting ambitious PPA ...
Phoenix, AZ · On-site
$135K - $139K/yr
Python Programming Language - * Physical Design Develop & own physical design implementation of multi-hierarchy low-power designs including physical-aware logic synthesis, design for testability ...
Phoenix, AZ · On-site
$135K - $139K/yr
Python Programming Language - * Physical Design Develop & own physical design implementation of multi-hierarchy low-power designs including physical-aware logic synthesis, design for testability ...
Austin, TX · On-site
$100K - $500K/yr
Tenstorrent is seeking a talented Physical Design Engineer to implement high-performance blocks for our industry-leading CPU and AI/ML architectures. You'll own the complete implementation flow from ...
Austin, TX · On-site
$100K - $500K/yr
Tenstorrent is seeking a talented Physical Design Engineer to implement high-performance blocks for our industry-leading CPU and AI/ML architectures. You'll own the complete implementation flow from ...
New York, NY · On-site
$148.80K - $153.20K/yr
About the Position We are looking to hire an ASIC Physical Design Engineer to help us design, test, and deploy advanced hardware. As part of our Ultra Low Latency team, you'll have the opportunity to ...
New York, NY · On-site
$148.80K - $153.20K/yr
About the Position We are looking to hire an ASIC Physical Design Engineer to help us design, test, and deploy advanced hardware. As part of our Ultra Low Latency team, you'll have the opportunity to ...
San Jose, CA · Hybrid
$159.40K - $164.10K/yr
ASIC Physical Design Engineer This role has been designed as 'Hybrid' with an expectation that you will work on average 2 days per week from an HPE office. Who We Are: Hewlett Packard Enterprise is ...
San Jose, CA · Hybrid
$159.40K - $164.10K/yr
ASIC Physical Design Engineer This role has been designed as 'Hybrid' with an expectation that you will work on average 2 days per week from an HPE office. Who We Are: Hewlett Packard Enterprise is ...
San Jose, CA · Hybrid
$159.40K - $164.10K/yr
ASIC Physical Design Engineer This role has been designed as 'Hybrid' with an expectation that you will work on average 2 days per week from an HPE office. Who We Are: Hewlett Packard Enterprise is ...
San Jose, CA · Hybrid
$159.40K - $164.10K/yr
ASIC Physical Design Engineer This role has been designed as 'Hybrid' with an expectation that you will work on average 2 days per week from an HPE office. Who We Are: Hewlett Packard Enterprise is ...
Austin, TX · On-site
$154.84K - $232.26K/yr
San Jose, CA/ Austin,TX (Hybrid) Employment Type: Full-Time About the Role We are seeking a Staff Physical Design Engineer to join our embedded FPGA (eFPGA) IP implementation team . In this role, you ...
Austin, TX · On-site
$154.84K - $232.26K/yr
San Jose, CA/ Austin,TX (Hybrid) Employment Type: Full-Time About the Role We are seeking a Staff Physical Design Engineer to join our embedded FPGA (eFPGA) IP implementation team . In this role, you ...
Saratoga, CA · On-site
$120K - $220K/yr
We are seeking a highly experienced Senior Physical Design Engineer to join our ASIC implementation ... a full time, exempt position, based out of our Saratoga office. The target base pay for this ...
Saratoga, CA · On-site
$120K - $220K/yr
We are seeking a highly experienced Senior Physical Design Engineer to join our ASIC implementation ... a full time, exempt position, based out of our Saratoga office. The target base pay for this ...
Eden Prairie, MN · On-site
$85K - $120K/yr
Eden Prairie, MN | Hybrid | Remote Schedule: Full-Time Salary: $85,000 - $120,000 (based on experience) EVS is seeking a Substation Physical Design Engineer to support the design and delivery of ...
Eden Prairie, MN · On-site
$85K - $120K/yr
Eden Prairie, MN | Hybrid | Remote Schedule: Full-Time Salary: $85,000 - $120,000 (based on experience) EVS is seeking a Substation Physical Design Engineer to support the design and delivery of ...
San Jose, CA · Hybrid
$159.40K - $164.10K/yr
ASIC Physical Design Engineer This role has been designed as 'Hybrid' with an expectation that you will work on average 2 days per week from an HPE office. Who We Are: Hewlett Packard Enterprise is ...
San Jose, CA · Hybrid
$159.40K - $164.10K/yr
ASIC Physical Design Engineer This role has been designed as 'Hybrid' with an expectation that you will work on average 2 days per week from an HPE office. Who We Are: Hewlett Packard Enterprise is ...
San Jose, CA · On-site
$154.84K - $232.26K/yr
San Jose, CA/ Austin,TX (Hybrid) Employment Type: Full-Time About the Role We are seeking a Staff Physical Design Engineer to join our embedded FPGA (eFPGA) IP implementation team . In this role, you ...
San Jose, CA · On-site
$154.84K - $232.26K/yr
San Jose, CA/ Austin,TX (Hybrid) Employment Type: Full-Time About the Role We are seeking a Staff Physical Design Engineer to join our embedded FPGA (eFPGA) IP implementation team . In this role, you ...
Saratoga, CA · On-site
$120K - $220K/yr
We are seeking a highly experienced Senior Physical Design Engineer to join our ASIC implementation ... a full time, exempt position, based out of our Saratoga office. The target base pay for this ...
Quick apply
Saratoga, CA · On-site
$120K - $220K/yr
We are seeking a highly experienced Senior Physical Design Engineer to join our ASIC implementation ... a full time, exempt position, based out of our Saratoga office. The target base pay for this ...
$95K - $99.2K
0% of jobs
$99.2K - $103.5K
0% of jobs
$103.5K - $107.7K
0% of jobs
$107.7K - $111.9K
0% of jobs
$111.9K - $116.1K
0% of jobs
$116.1K - $120.4K
0% of jobs
$120.4K - $124.6K
0% of jobs
$124.6K - $128.8K
0% of jobs
$128.8K - $133K
1% of jobs
$135.4K is the 25th percentile. Wages below this are outliers.
$133K - $137.3K
43% of jobs
The median wage is $137.7K / yr.
$137.3K - $141.5K
56% of jobs
$95K
$141.5K
| Aspect | Full Time Physical Design Engineer | Digital IC Design Engineer |
|---|---|---|
| Primary Focus | Physical implementation, layout, timing, power optimization | Logic design, architecture, HDL coding, functional verification |
| Skills & Certifications | EDA tools, CMOS fabrication, timing analysis | HDL languages (Verilog/VHDL), digital design principles |
| Work Environment | ASIC/SoC design teams, EDA tool suites | Design teams, simulation environments |
Full Time Physical Design Engineers focus on the physical implementation of integrated circuits, ensuring optimal layout and timing. Digital IC Design Engineers concentrate on creating and verifying digital logic designs. While both roles require knowledge of digital design, physical design emphasizes layout and fabrication considerations, making them distinct yet complementary roles in chip development.
$141.40K - $145.50K/yr
Full-time
Posted 28 days ago
NVIDIA has been transforming computer graphics, PC gaming, and accelerated computing for more than 25 years. It's a unique legacy of innovation that's fueled by great technology-and amazing people. Today, we're tapping into the unlimited potential of AI to define the next era of computing. An era in which our GPU acts as the brains of computers, robots, and self-driving cars that can understand the world. Doing what's never been done before takes vision, innovation, and the world's best talent. As an NVIDIAN, you'll be immersed in a diverse, supportive environment where everyone is inspired to do their best work. Come join the team and see how you can make a lasting impact on the world.
NVIDIA is looking for best-in-class Senior Physical Design Engineers to join our outstanding Networking Silicon engineering team, developing the industry's best high speed communication devices, delivering the highest throughput and lowest latency! Come and take a part in crafting our groundbreaking and innovating chips, enjoy working in a meaningful, growing and professional environment where you make a significant impact in a technology-focused company.
What you'll be doing:
You will lead all aspects of physical design and implementation of SOC devices targeted at the networking markets.
Work will be at the partition level.
As a member of a team, you will participate in establishing physical design methodologies, flow automation, chip floorplan, power/clock distribution, chip assembly and P&R, timing closure.
Daily work involves all aspects of physical chip development (RTL2GDS) - trial synthesis, power and clock distribution, place and route, timing closure, power and noise analysis and physical verification.
What we need to see:
BSEE / MSEE or equivalent experience.
3+ years of experience in VLSI physical design implementation on 5nm, 4nm and 3nm technology.
Able to assist in design flow development and debugging, including application of ML/AI solutions.
Already a validated strong power user of P&R, Timing Analysis, Physical Verification, IR Drop Analysis, CAD tools from Synopsys (ICC2/DC/PT/STAR/ICV), Cadence (Genus/Innovus/Tempus) and other major EDA companies.
Confirmed prior experience in timing closure, clock/power distribution and analysis, RC extraction and correlation, place/ route and tapeout solutions.
To be successful you should possess strong analytical and debugging skills.
Proficiency using Python, Perl, Tcl, Make scripting is helpful.
Great teammate
NVIDIA is widely considered to be the leader of AI computing, and one of the technology world's most desirable employers. We have some of the most forward-thinking and hardworking people in the world working for us. If you're creative and autonomous, we want to hear from you
Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. The base salary range is 116,000 USD - 189,750 USD for Level 2, and 136,000 USD - 218,500 USD for Level 3.You will also be eligible for equity and benefits.
This posting is for an existing vacancy.
NVIDIA uses AI tools in its recruiting processes.
NVIDIA is committed to fostering a diverse work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law.
Sourced by ZipRecruiter
NVIDIA has been transforming computer graphics, PC gaming, and accelerated computing for more than 25 years. It's a unique legacy of innovation that's fueled by great technology--and amazing people. Today, we're tapping into the unlimited potential of AI to define the next era of computing. An era in which our GPU acts as the brains of computers, robots, and self-driving cars that can understand the world. Doing what's never been done before takes vision, innovation, and the world's best talent.
Computer and electronic product manufacturing
10,000+ Employees
Santa Clara, CA, US
1993
