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Full Time Physical Design Engineer Jobs (NOW HIRING)

Physical Design Engineer

Austin, TX · On-site

$134K - $138K/yr

Hudson River Trading (HRT) is seeking a Physical Design Engineer with a broad, versatile skillset to join our growing Hardware team. In this role, you will help deliver performance-critical ASICs and ...

About the Role We are seeking a highly skilled Physical Design Engineer with deep expertise in physical design and methodology. This individual contributor role sits within our physical design team ...

Physical Design Engineer

Westford, MA · On-site

$141K - $145K/yr

NVIDIA is looking for best-in-class Senior Physical Design Engineers to join our outstanding Networking Silicon engineering team, developing the industry's best high speed communication devices ...

Physical Design Engineer

Westford, MA

$141K - $145K/yr

NVIDIA is looking for best-in-class Senior Physical Design Engineers to join our outstanding Networking Silicon engineering team, developing the industry's best high speed communication devices ...

Physical Design Engineer

San Jose, CA · On-site

$141K - $226K/yr

Broadcom is searching for an ASIC top level floorplan Physical Design Engineer to join the Asic Products Division. This position involves working with the latest technology to continue driving next ...

Physical Design Engineer

San Jose, CA · On-site

$141K - $226K/yr

Broadcom is searching for an ASIC top level floorplan Physical Design Engineer to join the Asic Products Division. This position involves working with the latest technology to continue driving next ...

Physical Design Engineer

Phoenix, AZ · On-site

$135K - $139K/yr

Python Programming Language - * Physical Design Develop & own physical design implementation of multi-hierarchy low-power designs including physical-aware logic synthesis, design for testability ...

CPU Physical Design Engineer

Beaverton, OR · On-site

$141K - $145K/yr

Description As a CPU Physical Design Engineer, you will drive or participate in the following: • Drive RTL-to-GDS design convergence through logic synthesis and place-and-route tools targeting ...

Physical Design Engineer

Austin, TX · On-site

$100K - $500K/yr

Tenstorrent is seeking a talented Physical Design Engineer to implement high-performance blocks for our industry-leading CPU and AI/ML architectures. You'll own the complete implementation flow from ...

CPU Physical Design Engineer

Beaverton, OR · On-site

$141K - $145K/yr

Description As a CPU Physical Design Engineer, you will drive or participate in the following: • Drive RTL-to-GDS design convergence through logic synthesis and place-and-route tools targeting ...

ASIC Physical Design Engineer

New York, NY · On-site

$148K - $153K/yr

About the Position We are looking to hire an ASIC Physical Design Engineer to help us design, test, and deploy advanced hardware. As part of our Ultra Low Latency team, you'll have the opportunity to ...

CPU Physical Design Engineer

Santa Clara, CA · On-site

$159K - $164K/yr

Description As a CPU Physical Design Engineer, you will drive or participate in the following: • Drive RTL-to-GDS design convergence through logic synthesis and place-and-route tools targeting ...

We are seeking a highly experienced Senior Physical Design Engineer to join our ASIC implementation ... a full time, exempt position, based out of our Saratoga office. The target base pay for this ...

Description As a Physical Design engineer you will contribute to all phases of physical design of high performance PHY design from RTL to delivery of our final GDSII. Your responsibilities include ...

We are seeking a highly experienced Senior Physical Design Engineer to join our ASIC implementation ... a full time, exempt position, based out of our Saratoga office. The target base pay for this ...

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Full Time Physical Design Engineer information

See salary details

$95K

$141.5K

How much do full time physical design engineer jobs pay per year?

As of Jul 9, 2026, the average yearly pay for full time physical design engineer in the United States is $139,408.00, according to ZipRecruiter salary data. Most workers in this role earn between $136,000.00 and $140,000.00 per year, depending on experience, location, and employer.

What is the difference between Full Time Physical Design Engineer vs Digital IC Design Engineer?

AspectFull Time Physical Design EngineerDigital IC Design Engineer
Primary FocusPhysical implementation, layout, timing, power optimizationLogic design, architecture, HDL coding, functional verification
Skills & CertificationsEDA tools, CMOS fabrication, timing analysisHDL languages (Verilog/VHDL), digital design principles
Work EnvironmentASIC/SoC design teams, EDA tool suitesDesign teams, simulation environments

Full Time Physical Design Engineers focus on the physical implementation of integrated circuits, ensuring optimal layout and timing. Digital IC Design Engineers concentrate on creating and verifying digital logic designs. While both roles require knowledge of digital design, physical design emphasizes layout and fabrication considerations, making them distinct yet complementary roles in chip development.

What cities are hiring for Full Time Physical Design Engineer jobs? Cities with the most Full Time Physical Design Engineer job openings:
What are the most commonly searched types of Physical Design Engineer jobs? The most popular types of Physical Design Engineer jobs are:
What states have the most Full Time Physical Design Engineer jobs? States with the most job openings for Full Time Physical Design Engineer jobs include:
Physical Design Engineer

Physical Design Engineer

Hudson River Trading

Austin, TX • On-site

$134K - $138K/yr

Full-time

Medical, Dental, Vision, Life, Retirement, PTO

Re-posted 11 days ago


Job description

Hudson River Trading (HRT) is seeking a Physical Design Engineer with a broad, versatile skillset to join our growing Hardware team. In this role, you will help deliver performance-critical ASICs and advance our physical design methodologies on leading-edge process nodes.
The Hardware team at HRT builds high-performance compute engines using FPGA and ASIC technology to drive low-latency trading decisions on global markets. We create custom solutions across the full spectrum of speed and sophistication, from bespoke circuits to world-class machine learning accelerators.
Responsibilities
  • Drive design-for-test (DFT) methodologies and implementation
  • Contribute to physical implementation, from RTL handoff through GDSII on advanced process nodes
  • Partner on floorplanning and physical optimization for high-performance, latency-critical designs
  • Close timing across multiple modes and corners while optimizing power, performance, and area (PPA)
  • Diagnose and resolve physical design issues such as timing bottlenecks, congestion, and IR/EM violations
  • Build, maintain, and improve repeatable, automated physical design flows
  • Develop scripts and tooling to improve productivity, robustness, and insight into design behavior
  • Collaborate closely with RTL, architecture, and other hardware engineers to influence design decisions early

Qualifications
  • Experience working in high-performance ASIC design environments
  • Strong fundamentals in digital logic, circuit design, and process technology
  • Familiarity with DFT concepts and testing methodologies
  • Strong scripting and automation skills (Python, Tcl, shell), including parsing and analyzing tool outputs
  • Ability to design robust methodologies, diagnose complex failures, and improve physical design flows
  • Applied use of statistics in analyzing timing, power, or design data (preferred)
  • Hands-on experience with static timing analysis and timing closure methodologies
  • Expertise using industry-standard physical design and signoff tools (e.g., Innovus, PrimeTime)

This job is accepting ongoing applications and there is no application deadline.
The estimated base salary range for this position is 200,000 to 300,000 USD per year (or local equivalent). The base pay offered may vary depending on multiple individualized factors, including location, job-related knowledge, skills, and experience.
This role will also be eligible for discretionary performance-based bonuses and a competitive benefits package which includes medical, dental, vision, basic life insurance, and enrollment in our company's retirement savings plans. Employees will receive sick and parental leave, as well as other paid time off (including 20 vacation days and 10 paid holidays in the US). Please note that benefits and time off policies will vary across non-US locations.
In any materials you submit, you may redact or remove age-identifying information such as age, date of birth, or dates of school attendance or graduation. You will not be penalized for redacting or removing this information.
Culture
Hudson River Trading (HRT) brings a scientific approach to trading financial products. We have built one of the world's most sophisticated computing environments for research and development. Our researchers are at the forefront of innovation in the world of algorithmic trading.
At HRT we welcome a variety of expertise: mathematics and computer science, physics and engineering, media and tech. We're a community of self-starters who are motivated by the excitement of being at the cutting edge of automation in every part of our organization-from trading, to business operations, to recruiting and beyond. We value openness and transparency, and celebrate great ideas from HRT veterans and new hires alike. At HRT we're friends and colleagues - whether we are sharing a meal, playing the latest board game, or writing elegant code. We embrace a culture of togetherness that extends far beyond the walls of our office.
Feel like you belong at HRT? Our goal is to find the best people and bring them together to do great work in a place where everyone is valued. HRT is proud of our diverse staff; we have offices all over the globe and benefit from our varied and unique perspectives. HRT is an equal opportunity employer; so whoever you are we'd love to get to know you.
Please be advised: Use of AI tools during interviews or assessments is strictly prohibited, unless otherwise instructed or agreed upon. We employ various methods to evaluate the authenticity of candidate responses. If we determine that AI assistance was used during any stage of the hiring process, we reserve the right to immediately disqualify your candidacy or rescind any job offers extended.