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Full Time Asic Rtl Design Engineer Jobs in North Carolina

Microsoft

Senior Physical Design Engineer

Raleigh, NC · On-site

$101K - $139K/yr

Responsible for RTL to GDS implementation in Physical Design domain for production flagship ... Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field AND ...

Rambus

MTS Digital Engineering

Morrisville, NC · Hybrid

$58K - $108K/yr

As a New College Graduate Design Engineer, the full-time position candidate will be responsible for specifying, architecting, implementing, and simulating RTL components. The individual will work ...

Rambus

MTS Digital Engineering

Morrisville, NC · Hybrid

$58K - $108K/yr

Overview As a New College Graduate Design Engineer, the full-time position candidate will be responsible for specifying, architecting, implementing, and simulating RTL components. The individual will ...

Nvidia

Senior ASIC Power Engineer

Durham, NC

We are now looking for a Senior ASIC Power Engineer! NVIDIA is seeking extraordinary power ... efficient RTL to achieve design targets * You will be working with architects, designers ...

Cadence Design Systems, Inc.

Lead Design Engineer

Cary, NC · On-site

$104K - $137K/yr

Work on RTL synthesis and floorplanning * Build clock trees and perform optimizations * Close ... Interface with Front End RTL design teams and Back End Verification teams Position Requirements ...

Nvidia

Senior ASIC Timing Engineer

Durham, NC

NVIDIA is looking for best-in-class Senior ASIC Timing Design Engineers to join our outstanding ... Help in driving frontend and backend implementation from RTL to gds2, including synthesis ...

Nvidia

Senior ASIC Verification Engineer

Durham, NC

NVIDIA is seeking outstanding ASIC Verification Engineer to verify the world's leading GPUs. This ... As a senior member of our verification team, you'll understand the design & implementation with ...

Nvidia

Senior ASIC Timing Engineer

Durham, NC · Hybrid

Work closely with RTL, DFX, Clocks, and other teams to devise timing closure strategies, create ... Experience in physical design and optimization e.g., synthesis, placement, routing, logic ...

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Full Time Asic Rtl Design Engineer information

What is a full time ASIC RTL design engineer?

Full Time ASIC RTL Design Engineers are professionals who specialize in designing digital circuits at the Register Transfer Level (RTL) for Application Specific Integrated Circuits (ASICs). They use hardware description languages like Verilog or VHDL to create, simulate, and verify complex digital systems that are manufactured as custom chips. Their work typically involves collaborating with other engineers to optimize performance, area, and power consumption, as well as ensuring that the design meets specified requirements. These engineers play a crucial role in the development of chips used in various applications, including consumer electronics, automotive systems, and telecommunications.

How much does a full time ASIC RTL design engineer make?

A full-time ASIC RTL design engineer typically earns between $100,000 and $150,000 annually, depending on experience, location, and company size. Senior engineers with specialized skills in hardware description languages like Verilog or VHDL may earn higher salaries, often exceeding $160,000.

What are the key skills and qualifications needed to thrive as a full time ASIC RTL design engineer, and why are they important?

To thrive as a Full Time ASIC RTL Design Engineer, you need a solid background in digital logic design, computer architecture, and proficiency in Hardware Description Languages (HDLs) like Verilog or VHDL, typically supported by a degree in electrical or computer engineering. Familiarity with EDA tools such as Synopsys, Cadence, or Mentor Graphics, and knowledge of simulation, synthesis, and timing analysis, are crucial, with some roles requiring verification or DFT experience. Strong analytical thinking, attention to detail, and effective communication skills set exceptional engineers apart in team environments. These skills and qualities are essential for creating reliable, efficient hardware designs and ensuring successful silicon implementations in a competitive technology landscape.

Are full time ASIC RTL design engineers in demand?

Full-time ASIC RTL design engineers are in high demand due to the growth of semiconductor and electronics industries, requiring expertise in hardware description languages like Verilog and VHDL. Companies seek professionals skilled in RTL design, verification, and FPGA prototyping to develop advanced integrated circuits for various applications.

What are some common challenges full time ASIC RTL design engineers face when collaborating with verification teams?

A common challenge for ASIC RTL Design Engineers is ensuring that the design specifications are interpreted consistently between design and verification teams. Misalignment can lead to time-consuming bug fixes and delays in the project schedule. Effective communication, regular design reviews, and close collaboration are vital to catching issues early and maintaining project momentum. Additionally, engineers must often adapt quickly to evolving requirements or last-minute changes, which requires flexibility and strong problem-solving skills.

What is the salary of a full time ASIC RTL design engineer?

The average salary for a full-time ASIC RTL design engineer typically ranges from $100,000 to $150,000 annually, depending on experience, location, and company size. Senior engineers with specialized skills in hardware description languages like Verilog or VHDL and experience with FPGA or ASIC design may earn higher compensation. Benefits often include performance bonuses, health insurance, and opportunities for professional development.
What are the most commonly searched types of Asic Rtl Design Engineer jobs in North Carolina? The most popular types of Asic Rtl Design Engineer jobs in North Carolina are:
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Full Time Asic Rtl Design Engineer jobs near you
Infographic showing various Full Time Asic Rtl Design Engineer job openings in North Carolina as of August 2026, with employment types broken down into 1% Internship, 85% Full Time, 10% Part Time, and 4% Contract. Highlights an 84% Physical, 5% Hybrid, and 11% Remote job distribution.

Senior Engineer, Design Verification

Marvell

Morrisville, NC • On-site

Full-time

Life, Retirement

This job post has expired 1 day ago. Applications are no longer accepted.

Job description

About Marvell

Marvell's semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities.

At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.

Your Team, Your Impact

Group Description
Marvell's CXL Product Development team works on groundbreaking innovations for the composable datacenter. We are looking for individuals with a deep understanding and passion for ASIC verification to craft creative solutions for DV architecture, verification and post-silicon validation on some of the industry's most complex semiconductor chips. If you're creative and autonomous, we want to hear from you! At Marvell, you will have the opportunity to shape some of the most incredible products to address the needs of the next generation datacenters.

What You Can Expect

Developverification plans for complex designs.Verifycomplex SoCs through simulation of register-transfer level (RTL) and gate level designs using industry standard tools and processes.Collaborate closely with design and other verification engineers to develop and implement verification test plans and drive verificationmethodologywork. Develop constrained-random verification test environment using Verilog/System Verilog, UVM and C programming, including testbenches, checkers, monitors, drivers and other testbench components.Use problem solving skills to debug failing simulations and create test vectors and testing scenarios to exhaustively exercise a design. Drive and analyze test coverage metrics.

What We're Looking For

BS in Electrical/Computer Engineering with 2 years of relevant experience

Or MS in Electrical/Computer Engineering

Must have work/internship experience or completed graduate coursework/research in each of the following:

Synopsys VCS (simulation).

Synopsys Verdi (debugging and waveform analysis).

Verilog, SystemVerilog, UVM.

C/C++ and Python scripting.

RTL Design Debug.

Functional Verification, Assertion-Based Verification, Constrained Random Verification.

AMBA AXI4 Protocol. PCIe fundamentals.

Developing test plans and coverage models. Advanced Computer Architecture concepts.

Expected Base Pay Range (USD)

97,700 - 144,410, $ per annum

The successful candidate's starting base pay will be determined based on job-related skills, experience, qualifications, work location and market conditions. The expected base pay range for this role may be modified based on market conditions.

Additional Compensation and Benefit Elements

Marvell is committed to providing exceptional, comprehensive benefits that support our employees at every stage - from internship to retirement and through life's most important moments. Our offerings are built around four key pillars: financial well-being, family support, mental and physical health, and recognition. Highlights include an employee stock purchase plan with a 2-year look back, family support programs to help balance work and home life, robust mental health resources to prioritize emotional well-being, and a recognition and service awards to celebrate contributions and milestones. We look forward to sharing more with you during the interview process.

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.

Any applicant who requires a reasonable accommodation during the selection process should contact Marvell HR Helpdesk at TAOps@marvell.com.

Interview Integrity

To support fair and authentic hiring practices, candidates are not permitted to use AI tools (such as transcription apps, real-time answer generators like ChatGPT or Copilot, or automated note-taking bots) during interviews.

These tools must not be used to record, assist with, or enhance responses in any way. Our interviews are designed to evaluate your individual experience, thought process, and communication skills in real time. Use of AI tools without prior instruction from the interviewer will result in disqualification from the hiring process.

This position may require access to technology and/or software subject to U.S. export control laws and regulations, including the Export Administration Regulations (EAR). As such, applicants must be eligible to access export-controlled information as defined under applicable law. Marvell may be required to obtain export licensing approval from the U.S. Department of Commerce and/or the U.S. Department of State. Except for U.S. citizens, lawful permanent residents, or protected individuals as defined by 8 U.S.C. 1324b(a)(3), all applicants may be subject to an export license review process prior to employment.

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