Description As a CPU Power Management Microarchitect/RTL Engineer, you will own or contribute to the following: • Micro-architecture development and specification - from early high-level ...
Description As a CPU Power Management Microarchitect/RTL Engineer, you will own or contribute to the following: • Micro-architecture development and specification - from early high-level ...
System IC Architect - Advanced Power Systems
Chandler, AZ · On-site +1
$239K/yr
This role emphasizes Advanced Power Management System IC Architecture for Point of Load (PoL ... This position can be done from anywhere in the United States and is open to 100% remote, however ...
System IC Architect - Advanced Power Systems
Chandler, AZ · On-site +1
$239K/yr
This role emphasizes Advanced Power Management System IC Architecture for Point of Load (PoL ... This position can be done from anywhere in the United States and is open to 100% remote, however ...
... from early arch definition, through bringup, to product release. Our ArchDev arm is a hub for all ... Minimum 10 years working on HSIO with the following capacity - power management, use case analysis ...
... from early arch definition, through bringup, to product release. Our ArchDev arm is a hub for all ... Minimum 10 years working on HSIO with the following capacity - power management, use case analysis ...
System level understanding of power management solutions for SoCs, CPUs, GPUs, FPGAs used in such ... Maintain a good understanding of competitive landscape from technology, and product definition ...
System level understanding of power management solutions for SoCs, CPUs, GPUs, FPGAs used in such ... Maintain a good understanding of competitive landscape from technology, and product definition ...
Support the development and execution of a targeted go-to-market plan for IPS Power Management ... from a home office with high travel demands (estimated 50-60%) A genuine relationship builder and ...
Support the development and execution of a targeted go-to-market plan for IPS Power Management ... from a home office with high travel demands (estimated 50-60%) A genuine relationship builder and ...
Support the development and execution of a targeted go-to-market plan for IPS Power Management ... from a home office with high travel demands (estimated 50-60%) A genuine relationship builder and ...
Support the development and execution of a targeted go-to-market plan for IPS Power Management ... from a home office with high travel demands (estimated 50-60%) A genuine relationship builder and ...
Support the development and execution of a targeted go-to-market plan for IPS Power Management ... from a home office with high travel demands (estimated 50-60%) A genuine relationship builder and ...
Support the development and execution of a targeted go-to-market plan for IPS Power Management ... from a home office with high travel demands (estimated 50-60%) A genuine relationship builder and ...
System level understanding of power management solutions for SoCs, CPUs, GPUs, FPGAs used in such ... Maintain a good understanding of competitive landscape from technology, and product definition ...
System level understanding of power management solutions for SoCs, CPUs, GPUs, FPGAs used in such ... Maintain a good understanding of competitive landscape from technology, and product definition ...
This position will provide leadership of the Power Electronics portfolio & Tower of Power platform ... from accredited institution * Five years relevant product management or application engineering ...
This position will provide leadership of the Power Electronics portfolio & Tower of Power platform ... from accredited institution * Five years relevant product management or application engineering ...
At least 10 years of relevant work experience in the Power Management industry with at least 7 ... autonomously from a home office with high travel demands (estimated 50-60%) • A genuine ...
At least 10 years of relevant work experience in the Power Management industry with at least 7 ... autonomously from a home office with high travel demands (estimated 50-60%) • A genuine ...
At least 10 years of relevant work experience in the Power Management industry with at least 7 ... autonomously from a home office with high travel demands (estimated 50-60%) • A genuine ...
At least 10 years of relevant work experience in the Power Management industry with at least 7 ... autonomously from a home office with high travel demands (estimated 50-60%) • A genuine ...
Design & Verification Engineer, Analog Power Management (7682)
Austin, TX · On-site
$197K/yr
TSMC's Power Management Research and Design Department, in Austin, TX, is looking for an ... from the U.S. Government for certain individuals. All employment is contingent upon TSMC North ...
Design & Verification Engineer, Analog Power Management (7682)
Austin, TX · On-site
$197K/yr
TSMC's Power Management Research and Design Department, in Austin, TX, is looking for an ... from the U.S. Government for certain individuals. All employment is contingent upon TSMC North ...
Design & Verification Engineer, Analog Power Management (7682)
Austin, TX · On-site
$197K/yr
TSMC's Power Management Research and Design Department, in Austin, TX, is looking for an ... from the U.S. Government for certain individuals. All employment is contingent upon TSMC North ...
Design & Verification Engineer, Analog Power Management (7682)
Austin, TX · On-site
$197K/yr
TSMC's Power Management Research and Design Department, in Austin, TX, is looking for an ... from the U.S. Government for certain individuals. All employment is contingent upon TSMC North ...
At least 10 years of relevant work experience in the Power Management industry with at least 7 ... autonomously from a home office with high travel demands (estimated 50-60%) • A genuine ...
At least 10 years of relevant work experience in the Power Management industry with at least 7 ... autonomously from a home office with high travel demands (estimated 50-60%) • A genuine ...
CPU Debug and Power Management Verification Engineer
Beaverton, OR · On-site
$141K/yr
... from pre-silicon test planning to supporting post-silicon bring-up and debug when needed. This role ... CPU Power Management, clock control, and debug logic • Develop and execute test plans and ...
CPU Debug and Power Management Verification Engineer
Beaverton, OR · On-site
$141K/yr
... from pre-silicon test planning to supporting post-silicon bring-up and debug when needed. This role ... CPU Power Management, clock control, and debug logic • Develop and execute test plans and ...
... power management systems. Responsibilities : • Develop and maintain software applications that ... from power system performance metrics. • Excellent communication and teamwork abilities, with a ...
... power management systems. Responsibilities : • Develop and maintain software applications that ... from power system performance metrics. • Excellent communication and teamwork abilities, with a ...
... from early arch definition, through bringup, to product release. Our ArchDev arm is a hub for all ... Minimum 10 years working on HSIO with the following capacity - power management, use case analysis ...
... from early arch definition, through bringup, to product release. Our ArchDev arm is a hub for all ... Minimum 10 years working on HSIO with the following capacity - power management, use case analysis ...
CPU Debug and Power Management Verification Engineer
Beaverton, OR · On-site
$141K/yr
... from pre-silicon test planning to supporting post-silicon bring-up and debug when needed. This role ... CPU Power Management, clock control, and debug logic • Develop and execute test plans and ...
CPU Debug and Power Management Verification Engineer
Beaverton, OR · On-site
$141K/yr
... from pre-silicon test planning to supporting post-silicon bring-up and debug when needed. This role ... CPU Power Management, clock control, and debug logic • Develop and execute test plans and ...
Implement CI/CD practices and manage deployment automation using tools such as Ansible or Terraform ... Strong data analysis skills to derive insights from power system performance metrics. * Excellent ...
Implement CI/CD practices and manage deployment automation using tools such as Ansible or Terraform ... Strong data analysis skills to derive insights from power system performance metrics. * Excellent ...
This position will provide leadership of the Power Electronics portfolio & Tower of Power platform ... from accredited institution * Five years relevant product management or application engineering ...
This position will provide leadership of the Power Electronics portfolio & Tower of Power platform ... from accredited institution * Five years relevant product management or application engineering ...
From Home Power Management information
See salary details
$13.22 - $16.74
18% of jobs
$18.17 is the 25th percentile. Wages below this are outliers.
$16.74 - $20.26
17% of jobs
The median wage is $22.31 / hr.
$20.26 - $23.78
26% of jobs
$26.94 is the 75th percentile. Wages above this are outliers.
$23.78 - $27.29
16% of jobs
$27.29 - $30.81
9% of jobs
$30.81 - $34.33
6% of jobs
$34.33 - $37.85
3% of jobs
$37.85 - $41.37
1% of jobs
$41.37 - $44.89
2% of jobs
$44.89 - $48.40
1% of jobs
$48.40 - $51.92
1% of jobs
$13
$25
$51
How much do from home power management jobs pay per hour?
As of Jul 15, 2026, the average hourly pay for from home power management in the United States is $25.61, according to ZipRecruiter salary data. Most workers in this role earn between $18.27 and $29.33 per hour, depending on experience, location, and employer.
What are the most commonly searched types of Power Management jobs? The most popular types of Power Management jobs are:
Full-time
Posted 14 days ago
Apple rating
8.1
Based on 670 frontline employees who took The Breakroom Quiz
5th of 30 rated technology retailers
Job description
Imagine what you could do here. At Apple, new ideas have a way of becoming extraordinary products, services and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could accomplish. Dynamic, hard-working people and inspiring, innovative technologies are the norm here. The people who work here have reinvented entire industries with all Apple Hardware products! The same passion for innovation that goes into our products also applies to our practices strengthening our commitment to leave the world better than we found it. Do you want to join us in these pursuits? Join us to help deliver the next groundbreaking Apple product!
Apple's Silicon Engineering Group (SEG) designs high-performance, low power microprocessors that power our innovative products, including the iPhone, iPad, Watch, Vision Pro, and Mac. We are looking for an experienced engineer to help drive architecture and RTL for world-class CPU power management solutions.
Description
As a CPU Power Management Microarchitect/RTL Engineer, you will own or contribute to the following:
• Micro-architecture development and specification - from early high-level architectural exploration, through micro-architectural research and arriving at a detailed specification
• RTL ownership - development, assessment and refinement of RTL design to target power, performance, area and timing goals
• Verification - support the verification team in test bench development, formal methods, and simulation/emulation for functional verification
• Performance exploration and correlation - explore high-performance strategies and work with the performance verification team to verify that the RTL design meets targeted performance
• Design delivery - work with multi-functional engineering team to implement and verify physical design on the aspects of timing, area, reliability, testability and power
Minimum Qualifications
Minimum BS and 3+ years of relevant industry experience
Experience with microprocessor architecture
Experience with logic design principles with timing and power implications
Experience in Verilog or VHDL
Experience with simulators and waveform debugging process
Preferred Qualifications
Expertise in one or more of the following areas: dynamic voltage and frequency scaling (DVFS/DVFM), advanced thermal and energy management, power state definition and management, dynamic clocking solutions, Di/dt mitigation strategies, micro-architecture strategies for improved power integrity, debug solutions, error handling, reset control, clock generation and asynchronous clock crossing strategies
Understanding of low power microarchitecture techniques
Understanding of high-performance techniques and trade-offs in a CPU microarchitecture
Experience in C or C++ programming
Experience using an interpretive language such as Perl or Python
Apple's Silicon Engineering Group (SEG) designs high-performance, low power microprocessors that power our innovative products, including the iPhone, iPad, Watch, Vision Pro, and Mac. We are looking for an experienced engineer to help drive architecture and RTL for world-class CPU power management solutions.
Description
As a CPU Power Management Microarchitect/RTL Engineer, you will own or contribute to the following:
• Micro-architecture development and specification - from early high-level architectural exploration, through micro-architectural research and arriving at a detailed specification
• RTL ownership - development, assessment and refinement of RTL design to target power, performance, area and timing goals
• Verification - support the verification team in test bench development, formal methods, and simulation/emulation for functional verification
• Performance exploration and correlation - explore high-performance strategies and work with the performance verification team to verify that the RTL design meets targeted performance
• Design delivery - work with multi-functional engineering team to implement and verify physical design on the aspects of timing, area, reliability, testability and power
Minimum Qualifications
Minimum BS and 3+ years of relevant industry experience
Experience with microprocessor architecture
Experience with logic design principles with timing and power implications
Experience in Verilog or VHDL
Experience with simulators and waveform debugging process
Preferred Qualifications
Expertise in one or more of the following areas: dynamic voltage and frequency scaling (DVFS/DVFM), advanced thermal and energy management, power state definition and management, dynamic clocking solutions, Di/dt mitigation strategies, micro-architecture strategies for improved power integrity, debug solutions, error handling, reset control, clock generation and asynchronous clock crossing strategies
Understanding of low power microarchitecture techniques
Understanding of high-performance techniques and trade-offs in a CPU microarchitecture
Experience in C or C++ programming
Experience using an interpretive language such as Perl or Python
About Apple
Sourced by ZipRecruiter
Imagine what you could do here! At Apple, new ideas have a way of becoming extraordinary products, services, and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could accomplish. Dynamic, intelligent people and inspiring, innovative technologies are the norm here. The people who work here have reinvented entire industries with all Apple Hardware products. The same real passion for innovation that goes into our products also applies to our practices strengthening our dedication to leave the world better than we found it.
Industry
Computer and electronic product manufacturing
Company size
10,000+ Employees
Headquarters location
Cupertino, CA, US
Year founded
1976