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Freelance Asic Rtl Design Engineer Jobs in Spartanburg, SC

AERONIX INC

Senior FPGA Design Engineer

Greenville, SC · On-site

$145K - $175K/yr

ROLE We are seeking a Senior FPGA Design Engineer with at least 10 years of experience to develop ... Lead full life-cycle FPGA development, from requirements and architecture through RTL ...

AERONIX INC

Senior FPGA Design Engineer

Greenville, SC · On-site

$145K - $175K/yr

ROLE We are seeking a Senior FPGA Design Engineer with at least 10 years of experience to develop ... Lead full life-cycle FPGA development, from requirements and architecture through RTL ...

AERONIX INC

Senior FPGA Design Engineer

Greenville, SC · On-site

$145K - $175K/yr

ROLE We are seeking a Senior FPGA Design Engineer with at least 10 years of experience to develop ... Lead full life-cycle FPGA development, from requirements and architecture through RTL ...

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Freelance Asic Rtl Design Engineer information

See Spartanburg, SC salary details

$14

$46

$129

How much do freelance asic rtl design engineer jobs pay per hour?

As of Sep 5, 2026, the average hourly pay for freelance asic rtl design engineer in Spartanburg, SC is $46.61, according to ZipRecruiter salary data. Most workers in this role earn between $23.70 and $60.34 per hour, depending on experience, location, and employer.

Are freelance ASIC RTL design engineers in demand?

Freelance ASIC RTL design engineers are in demand due to the growing need for custom chip development in industries like telecommunications, AI, and consumer electronics. Skills in hardware description languages such as Verilog or VHDL, along with experience in FPGA prototyping, enhance employability in this flexible work arrangement.

How much does a Freelance ASIC RTL Design Engineer make?

Freelance ASIC RTL Design Engineers typically earn between $50 and $150 per hour, depending on experience, project complexity, and location. Rates can vary based on expertise in hardware description languages like Verilog or VHDL and familiarity with FPGA or ASIC design tools.

What are the most commonly searched types of Asic Rtl Design Engineer jobs in Spartanburg, SC?

The most popular types of Asic Rtl Design Engineer jobs in Spartanburg, SC are:

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For Freelance Asic Rtl Design Engineer jobs in Spartanburg, SC, the most frequently searched job titles are:

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Freelance Asic Rtl Design Engineer jobs near you
Infographic showing various Freelance Asic Rtl Design Engineer job openings in Spartanburg, SC as of August 2026, with employment types broken down into 70% Full Time, 3% Temporary, and 27% Contract. Highlights an 87% In-person, and 13% Remote job distribution, with an average salary of $96,951 per year, or $46.6 per hour.

Senior FPGA Design Engineer

AERONIX INC

Greenville, SC • On-site

$145K - $175K/yr

Other

This job post has expired today. Applications are no longer accepted.

Job description

Job Description
Job Description


Job Title: Senior FPGA Engineer
Department: Engineering
Reports To: Functional Team Lead / Program Manager
FLSA Status: Exempt / Full-time

Salary Range: $145k - $175k Annually

DoD Secret clearance (or higher) REQUIRED.


ROLE

We are seeking a Senior FPGA Design Engineer with at least 10 years of experience to develop the architecture, implementation, and verification of complex, high-speed FPGA solutions. The ideal candidate will have deep expertise in high-bandwidth interfaces such as PCIe Gen4/5, 10 to 100G+ Ethernet, and DDR4/DDR5, along with strong skills in RTL design (VHDL/Verilog/ SystemVerilog), timing closure, and signal integrity. Experience with Cryptography, DSP and RF applications is strong plus. This role involves driving FPGA design from concept through production, integrating vendor IP, optimizing for low latency and high throughput, and performing rigorous verification and lab validation. The engineer will collaborate across hardware and software teams, mentor junior engineers, and ensure designs meet stringent reliability and compliance standards.

RESPONSIBILITIES

  • Lead full life-cycle FPGA development, from requirements and architecture through RTL implementation (Verilog/VHDL), verification, and system integration across multiple FPGA families.
  • Define and document FPGA architecture, including block diagrams, clocking strategies, and trade-off analyses; participate in and conduct design reviews.
  • Develop robust, reusable, and self-checking testbenches; implement functional coverage models and achieve code coverage closure.
  • Create and execute detailed test plans, procedures, and reports; ensure verification rigor and traceability.
  • Collaborate with hardware and software teams to integrate FPGA designs at the board and system level; support lab bring-up, debug, and qualification testing.
  • Implement and validate JTAG boundary scan and other DFT features; ensure compliance with design-for-test and reliability standards.
  • Drive continuous improvement in design practices, coding standards, and verification methodologies; mentor junior engineers and contribute to technical reviews.

REQUIRED SKILLS

  • Strong proficiency in RTL design using Verilog/VHDL, including custom implementations beyond vendor IP integration.
  • Strong experience in testbench development, functional coverage, and verification of complex FPGA designs.
  • Proficient with FPGA simulation and synthesis tools (e.g., QuestaSim, ModelSim, Riviera-PRO, Xilinx Vivado, Intel Quartus).
  • Proficiency of FPGA architecture and optimization techniques for timing closure, floor-planning, and resource utilization.
  • Ability to perform FPGA power estimation and analysis using vendor tools and optimize designs for power and thermal constraints.
  • Strong understanding of high-speed interfaces (PCIe, Ethernet, Serial RapidIO, DDRx) and control protocols (I²C, SPI, RS-232/422).
  • Experience with System-on-Chip technologies.

PREFERRED SKILLS

  • Proficiency in FPGA Block Design development and debugging (e.g., Vivado, Libero).
  • Familiarity with Universal Verification Methodology (UVM).
  • Familiarity with Microsemi Libero and Lattus Diamond.
  • Familiarity with revision control systems (Git/Bitbucket) and scripting in Python, TCL, or Linux shell for automation.
  • Skilled in FPGA lab validation using oscilloscopes, logic analyzers, and protocol analyzers.
  • Support JTAG Boundary scan design and testing
  • Experience with Cryptography, Digital Signal Processing and RF Applications
  • MATLAB modeling
  • Strong oral and written communication skills, with ability to document and present technical work clearly.
  • Experience collaborating in Agile environments and using tools like Jira and requirements management systems (e.g., Jama).
  • Familiarity with Manufacturing processes, and Electronic Stress Screening.
  • Understanding of formal verification processes and compliance standards.

QUALIFICATIONS

  • Bachelor’s Degree in Electrical Engineering, Computer Engineering, or related field.
  • Minimum 10 years of relevant experience in FPGA design.
  • Excellent written and verbal communication skills.
  • Ability to work in a collaborative team environment.
  • DoD Secret clearance (or higher) REQUIRED.
  • Position located in Melbourne, FL or Greenville, SC (not remote).


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