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Formal Verification Research Engineer Jobs (NOW HIRING)

Formal Verification Engineer

San Diego, CA · On-site

$144K/yr

... Formal Verification is a must Qualifications Experience in functional verification EDA tools: VCS, IUS, ModelSim, Jasper, 0-in, IFV, OneSpin, SLEC, etc is highly desired - Familiar with programming ...

Formal Verification - AI/ML Engineer

Austin, TX · On-site

$134K/yr

Apple's Hardware Technologies Formal Verification team is seeking an AI/ML Engineer to work at the ... ML research into practical, production-quality tools and workflows used by the FV team ...

Formal Verification - AI/ML Engineer

Austin, TX · On-site

$134K/yr

Apple's Hardware Technologies Formal Verification team is seeking an AI/ML Engineer to work at the ... Evaluating and integrating emerging AI/ML research into practical, production-quality tools and ...

Apply formal verification techniques using Lean or similar frameworks to formally verify safety ... Proven track record in research or development of programming languages * Proven track record of ...

Apple's Hardware Technologies Formal Verification team is seeking an AI/ML Engineer to work at the ... Evaluating and integrating emerging AI/ML research into practical, production-quality tools and ...

Apple's Hardware Technologies Formal Verification team is seeking an AI/ML Engineer to work at the ... Evaluating and integrating emerging AI/ML research into practical, production-quality tools and ...

... Engineering Group > CPU EngineeringGeneral Summary:Are you interested in working with a world-class CPU design team? Are you interested in the application of formal methods to the verification of ...

Showing results 41-60

Formal Verification Research Engineer information

See salary details

$80K

$142.6K

$203.5K

How much do formal verification research engineer jobs pay per year?

As of Sep 10, 2026, the average yearly pay for formal verification research engineer in the United States is $142,619.00, according to ZipRecruiter salary data. Most workers in this role earn between $136,000.00 and $136,000.00 per year, depending on experience, location, and employer.

What are popular job titles related to Formal Verification Research Engineer jobs?

For Formal Verification Research Engineer jobs, the most frequently searched job titles are:

Infographic showing various Formal Verification Research Engineer job openings in the United States as of September 2026, with employment types broken down into 1% Internship, 1% As Needed, 88% Full Time, 9% Part Time, and 1% Contract. Highlights an 79% Physical, 3% Hybrid, and 18% Remote job distribution, with an average salary of $142,619 per year, or $68.6 per hour.

Formal Verification Engineer

San Diego, CA • On-site

$144K/yr

Full-time

Re-posted just now


Job description

Company Description

About Mirafra :
Mirafra is software service base organization started in 2004.

     We are 500+ employees in India and 250+ In US
    Clear visibility to senior management which helps for constant professional growth

Job Description

Experience with the following: - ASIC design process, digital design, design (hw/sw) verification tools and techniques, computer architecture, etc. -Design and assertion languages: VHDL, Verilog, System Verilog, and System Verilog Assertions (SVA), Experience with Formal Verification is a must


Qualifications

Experience in functional verification EDA tools: VCS, IUS, ModelSim, Jasper, 0-in, IFV, OneSpin, SLEC, etc is highly desired - Familiar with programming languages: C, C++, and SystemC - Scripting and automation skills: Unix/Linux shell programming, Perl, Java, Makefile, XML, XML DOM, XPath, XSLT, revision management (e.g. CVS, DesignSync, Subversion

Additional Information

All your information will be kept confidential according to EEO guidelines.